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cpu_loop_exit: avoid using AREG0

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Make cpu_loop_exit() take a parameter for CPUState instead of relying
on global env.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2011-05-14 12:52:35 +00:00
parent 4d2c2b77f3
commit 1162c041c1
16 changed files with 57 additions and 56 deletions
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16
cpu-exec.c
View File

@ -37,10 +37,10 @@ int qemu_cpu_has_work(CPUState *env)
return cpu_has_work(env);
}
void cpu_loop_exit(void)
void cpu_loop_exit(CPUState *env1)
{
env->current_tb = NULL;
longjmp(env->jmp_env, 1);
env1->current_tb = NULL;
longjmp(env1->jmp_env, 1);
}
/* exit the current TB from a signal handler. The host registers are
@ -327,7 +327,7 @@ int cpu_exec(CPUState *env1)
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
env->exception_index = EXCP_DEBUG;
cpu_loop_exit();
cpu_loop_exit(env);
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
@ -336,7 +336,7 @@ int cpu_exec(CPUState *env1)
env->interrupt_request &= ~CPU_INTERRUPT_HALT;
env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit();
cpu_loop_exit(env);
}
#endif
#if defined(TARGET_I386)
@ -344,7 +344,7 @@ int cpu_exec(CPUState *env1)
svm_check_intercept(SVM_EXIT_INIT);
do_cpu_init(env);
env->exception_index = EXCP_HALTED;
cpu_loop_exit();
cpu_loop_exit(env);
} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
do_cpu_sipi(env);
} else if (env->hflags2 & HF2_GIF_MASK) {
@ -564,7 +564,7 @@ int cpu_exec(CPUState *env1)
if (unlikely(env->exit_request)) {
env->exit_request = 0;
env->exception_index = EXCP_INTERRUPT;
cpu_loop_exit();
cpu_loop_exit(env);
}
#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
@ -647,7 +647,7 @@ int cpu_exec(CPUState *env1)
}
env->exception_index = EXCP_INTERRUPT;
next_tb = 0;
cpu_loop_exit();
cpu_loop_exit(env);
}
}
}

2
exec-all.h
View File

@ -95,7 +95,7 @@ TranslationBlock *tb_gen_code(CPUState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
void cpu_exec_init(CPUState *env);
void QEMU_NORETURN cpu_loop_exit(void);
void QEMU_NORETURN cpu_loop_exit(CPUState *env1);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);

6
target-alpha/op_helper.c
View File

@ -32,7 +32,7 @@ void QEMU_NORETURN helper_excp(int excp, int error)
{
env->exception_index = excp;
env->error_code = error;
cpu_loop_exit();
cpu_loop_exit(env);
}
static void do_restore_state(void *retaddr)
@ -53,7 +53,7 @@ static void QEMU_NORETURN dynamic_excp(int excp, int error)
env->exception_index = excp;
env->error_code = error;
do_restore_state(GETPC());
cpu_loop_exit();
cpu_loop_exit(env);
}
static void QEMU_NORETURN arith_excp(int exc, uint64_t mask)
@ -1341,7 +1341,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
if (unlikely(ret != 0)) {
do_restore_state(retaddr);
/* Exception index and error code are already set */
cpu_loop_exit();
cpu_loop_exit(env);
}
env = saved_env;
}

6
target-arm/op_helper.c
View File

@ -25,7 +25,7 @@
void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
cpu_loop_exit(env);
}
uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
@ -234,13 +234,13 @@ void HELPER(wfi)(void)
{
env->exception_index = EXCP_HLT;
env->halted = 1;
cpu_loop_exit();
cpu_loop_exit(env);
}
void HELPER(exception)(uint32_t excp)
{
env->exception_index = excp;
cpu_loop_exit();
cpu_loop_exit(env);
}
uint32_t HELPER(cpsr_read)(void)

4
target-cris/op_helper.c
View File

@ -83,7 +83,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
helper_top_evaluate_flags();
}
}
cpu_loop_exit();
cpu_loop_exit(env);
}
env = saved_env;
}
@ -93,7 +93,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
void helper_raise_exception(uint32_t index)
{
env->exception_index = index;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_tlb_flush_pid(uint32_t pid)

16
target-i386/op_helper.c
View File

@ -1000,7 +1000,7 @@ void helper_syscall(int next_eip_addend)
{
env->exception_index = EXCP_SYSCALL;
env->exception_next_eip = env->eip + next_eip_addend;
cpu_loop_exit();
cpu_loop_exit(env);
}
#else
void helper_syscall(int next_eip_addend)
@ -1335,7 +1335,7 @@ static void QEMU_NORETURN raise_interrupt(int intno, int is_int, int error_code,
env->error_code = error_code;
env->exception_is_int = is_int;
env->exception_next_eip = env->eip + next_eip_addend;
cpu_loop_exit();
cpu_loop_exit(env);
}
/* shortcuts to generate exceptions */
@ -4658,7 +4658,7 @@ static void do_hlt(void)
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_hlt(int next_eip_addend)
@ -4696,7 +4696,7 @@ void helper_mwait(int next_eip_addend)
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_reset_rf(void)
@ -5048,7 +5048,7 @@ void helper_vmrun(int aflag, int next_eip_addend)
env->exception_is_int = 0;
env->exception_next_eip = EIP;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI");
cpu_loop_exit();
cpu_loop_exit(env);
break;
case SVM_EVTINJ_TYPE_EXEPT:
env->exception_index = vector;
@ -5056,7 +5056,7 @@ void helper_vmrun(int aflag, int next_eip_addend)
env->exception_is_int = 0;
env->exception_next_eip = -1;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT");
cpu_loop_exit();
cpu_loop_exit(env);
break;
case SVM_EVTINJ_TYPE_SOFT:
env->exception_index = vector;
@ -5064,7 +5064,7 @@ void helper_vmrun(int aflag, int next_eip_addend)
env->exception_is_int = 1;
env->exception_next_eip = EIP;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT");
cpu_loop_exit();
cpu_loop_exit(env);
break;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", env->exception_index, env->error_code);
@ -5400,7 +5400,7 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
env->error_code = 0;
env->old_exception = -1;
cpu_loop_exit();
cpu_loop_exit(env);
}
#endif

6
target-lm32/op_helper.c
View File

@ -20,14 +20,14 @@
void helper_raise_exception(uint32_t index)
{
env->exception_index = index;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_hlt(void)
{
env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_wcsr_im(uint32_t im)
@ -98,7 +98,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
cpu_restore_state(tb, env, pc);
}
}
cpu_loop_exit();
cpu_loop_exit(env);
}
env = saved_env;
}

6
target-m68k/op_helper.c
View File

@ -71,7 +71,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
cpu_restore_state(tb, env, pc);
}
}
cpu_loop_exit();
cpu_loop_exit(env);
}
env = saved_env;
}
@ -118,7 +118,7 @@ void do_interrupt(int is_hw)
}
env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit();
cpu_loop_exit(env);
return;
}
if (env->exception_index >= EXCP_TRAP0
@ -160,7 +160,7 @@ void do_interrupt(int is_hw)
static void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
cpu_loop_exit(env);
}
void HELPER(raise_exception)(uint32_t tt)

4
target-microblaze/op_helper.c
View File

@ -63,7 +63,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
cpu_restore_state(tb, env, pc);
}
}
cpu_loop_exit();
cpu_loop_exit(env);
}
env = saved_env;
}
@ -107,7 +107,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
void helper_raise_exception(uint32_t index)
{
env->exception_index = index;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_debug(void)

4
target-mips/op_helper.c
View File

@ -38,7 +38,7 @@ void helper_raise_exception_err (uint32_t exception, int error_code)
#endif
env->exception_index = exception;
env->error_code = error_code;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_raise_exception (uint32_t exception)
@ -277,7 +277,7 @@ static inline target_phys_addr_t do_translate_address(target_ulong address, int
lladdr = cpu_mips_translate_address(env, address, rw);
if (lladdr == -1LL) {
cpu_loop_exit();
cpu_loop_exit(env);
} else {
return lladdr;
}

2
target-ppc/op_helper.c
View File

@ -44,7 +44,7 @@ void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
#endif
env->exception_index = exception;
env->error_code = error_code;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_raise_exception (uint32_t exception)

12
target-s390x/op_helper.c
View File

@ -73,7 +73,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
cpu_restore_state(tb, env, pc);
}
}
cpu_loop_exit();
cpu_loop_exit(env);
}
env = saved_env;
}
@ -92,7 +92,7 @@ void HELPER(exception)(uint32_t excp)
{
HELPER_LOG("%s: exception %d\n", __FUNCTION__, excp);
env->exception_index = excp;
cpu_loop_exit();
cpu_loop_exit(env);
}
#ifndef CONFIG_USER_ONLY
@ -2326,7 +2326,7 @@ void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
void HELPER(load_psw)(uint64_t mask, uint64_t addr)
{
load_psw(env, mask, addr);
cpu_loop_exit();
cpu_loop_exit(env);
}
static void program_interrupt(CPUState *env, uint32_t code, int ilc)
@ -2341,7 +2341,7 @@ static void program_interrupt(CPUState *env, uint32_t code, int ilc)
env->int_pgm_code = code;
env->int_pgm_ilc = ilc;
env->exception_index = EXCP_PGM;
cpu_loop_exit();
cpu_loop_exit(env);
}
}
@ -2828,12 +2828,12 @@ static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
}
if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) {
cpu_loop_exit();
cpu_loop_exit(env);
}
dest |= a1 & ~TARGET_PAGE_MASK;
if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) {
cpu_loop_exit();
cpu_loop_exit(env);
}
src |= a2 & ~TARGET_PAGE_MASK;

10
target-sh4/op_helper.c
View File

@ -66,7 +66,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
if (ret) {
/* now we have a real cpu fault */
cpu_restore_state_from_retaddr(retaddr);
cpu_loop_exit();
cpu_loop_exit(env);
}
env = saved_env;
}
@ -87,7 +87,7 @@ static inline void raise_exception(int index, void *retaddr)
{
env->exception_index = index;
cpu_restore_state_from_retaddr(retaddr);
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_raise_illegal_instruction(void)
@ -113,7 +113,7 @@ void helper_raise_slot_fpu_disable(void)
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_sleep(uint32_t next_pc)
@ -122,7 +122,7 @@ void helper_sleep(uint32_t next_pc)
env->in_sleep = 1;
env->exception_index = EXCP_HLT;
env->pc = next_pc;
cpu_loop_exit();
cpu_loop_exit(env);
}
void helper_trapa(uint32_t tra)
@ -482,7 +482,7 @@ static void update_fpscr(void *retaddr)
if (cause & enable) {
cpu_restore_state_from_retaddr(retaddr);
env->exception_index = 0x120;
cpu_loop_exit();
cpu_loop_exit(env);
}
}
}

6
target-sparc/op_helper.c
View File

@ -316,7 +316,7 @@ static inline target_ulong asi_address_mask(CPUState *env1,
static void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
cpu_loop_exit(env);
}
void HELPER(raise_exception)(int tt)
@ -3724,7 +3724,7 @@ void helper_ldxfsr(uint64_t new_fsr)
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
cpu_loop_exit();
cpu_loop_exit(env);
}
#ifndef TARGET_SPARC64
@ -4424,7 +4424,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
if (ret) {
cpu_restore_state2(retaddr);
cpu_loop_exit();
cpu_loop_exit(env);
}
env = saved_env;
}

2
target-unicore32/op_helper.c
View File

@ -16,7 +16,7 @@
void HELPER(exception)(uint32_t excp)
{
env->exception_index = excp;
cpu_loop_exit();
cpu_loop_exit(env);
}
static target_ulong asr_read(void)

11
user-exec.c
View File

@ -37,13 +37,14 @@
//#define DEBUG_SIGNAL
static void exception_action(CPUState *env1)
{
#if defined(TARGET_I386)
#define EXCEPTION_ACTION \
raise_exception_err(env->exception_index, env->error_code)
raise_exception_err(env1->exception_index, env1->error_code);
#else
#define EXCEPTION_ACTION \
cpu_loop_exit()
cpu_loop_exit(env1);
#endif
}
/* exit the current TB from a signal handler. The host registers are
restored in a state compatible with the CPU emulator
@ -118,7 +119,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL);
EXCEPTION_ACTION;
exception_action(env);
/* never comes here */
return 1;