target/mips: Add emulation of nanoMIPS 32-bit branch instructions
Add emulation of various flavors of nanoMIPS 32-bit branch instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Stefan Markovic
Aleksandar Markovic
parent
0b16dcd180
commit
11d0fc10b7
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@ -17217,6 +17217,321 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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/* Immediate Value Compact Branches */
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static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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int rt, int32_t imm, int32_t offset)
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{
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TCGCond cond;
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int bcond_compute = 0;
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_load_gpr(t0, rt);
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tcg_gen_movi_tl(t1, imm);
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ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
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/* Load needed operands and calculate btarget */
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switch (opc) {
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case NM_BEQIC:
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if (rt == 0 && imm == 0) {
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/* Unconditional branch */
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} else if (rt == 0 && imm != 0) {
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/* Treat as NOP */
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goto out;
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} else {
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bcond_compute = 1;
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cond = TCG_COND_EQ;
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}
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break;
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case NM_BBEQZC:
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case NM_BBNEZC:
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if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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} else if (rt == 0 && opc == NM_BBEQZC) {
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/* Unconditional branch */
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} else if (rt == 0 && opc == NM_BBNEZC) {
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/* Treat as NOP */
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goto out;
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} else {
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tcg_gen_shri_tl(t0, t0, imm);
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tcg_gen_andi_tl(t0, t0, 1);
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tcg_gen_movi_tl(t1, 0);
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bcond_compute = 1;
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if (opc == NM_BBEQZC) {
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cond = TCG_COND_EQ;
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} else {
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cond = TCG_COND_NE;
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}
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}
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break;
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case NM_BNEIC:
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if (rt == 0 && imm == 0) {
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/* Treat as NOP */
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goto out;
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} else if (rt == 0 && imm != 0) {
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/* Unconditional branch */
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} else {
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bcond_compute = 1;
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cond = TCG_COND_NE;
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}
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break;
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case NM_BGEIC:
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if (rt == 0 && imm == 0) {
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/* Unconditional branch */
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} else {
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bcond_compute = 1;
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cond = TCG_COND_GE;
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}
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break;
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case NM_BLTIC:
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bcond_compute = 1;
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cond = TCG_COND_LT;
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break;
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case NM_BGEIUC:
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if (rt == 0 && imm == 0) {
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/* Unconditional branch */
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} else {
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bcond_compute = 1;
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cond = TCG_COND_GEU;
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}
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break;
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case NM_BLTIUC:
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bcond_compute = 1;
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cond = TCG_COND_LTU;
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break;
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default:
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MIPS_INVAL("Immediate Value Compact branch");
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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}
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if (bcond_compute == 0) {
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/* Uncoditional compact branch */
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gen_goto_tb(ctx, 0, ctx->btarget);
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} else {
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/* Conditional compact branch */
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TCGLabel *fs = gen_new_label();
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tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, t1, fs);
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gen_goto_tb(ctx, 1, ctx->btarget);
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gen_set_label(fs);
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gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
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}
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out:
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */
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static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
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int rt)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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/* load rs */
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gen_load_gpr(t0, rs);
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/* link */
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if (rt != 0) {
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tcg_gen_movi_tl(cpu_gpr[rt], ctx->base.pc_next + 4);
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}
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/* calculate btarget */
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tcg_gen_shli_tl(t0, t0, 1);
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tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
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gen_op_addr_add(ctx, btarget, t1, t0);
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/* unconditional branch to register */
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tcg_gen_mov_tl(cpu_PC, btarget);
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tcg_gen_lookup_and_goto_ptr();
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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/* nanoMIPS Branches */
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static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
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int rs, int rt, int32_t offset)
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{
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int bcond_compute = 0;
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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/* Load needed operands and calculate btarget */
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switch (opc) {
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/* compact branch */
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case OPC_BGEC:
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case OPC_BLTC:
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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bcond_compute = 1;
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ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
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break;
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case OPC_BGEUC:
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case OPC_BLTUC:
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if (rs == 0 || rs == rt) {
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/* OPC_BLEZALC, OPC_BGEZALC */
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/* OPC_BGTZALC, OPC_BLTZALC */
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tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4);
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}
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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bcond_compute = 1;
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ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
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break;
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case OPC_BC:
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ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
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break;
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case OPC_BEQZC:
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if (rs != 0) {
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/* OPC_BEQZC, OPC_BNEZC */
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gen_load_gpr(t0, rs);
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bcond_compute = 1;
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ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
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} else {
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/* OPC_JIC, OPC_JIALC */
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TCGv tbase = tcg_temp_new();
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TCGv toffset = tcg_temp_new();
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gen_load_gpr(tbase, rt);
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tcg_gen_movi_tl(toffset, offset);
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gen_op_addr_add(ctx, btarget, tbase, toffset);
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tcg_temp_free(tbase);
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tcg_temp_free(toffset);
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}
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break;
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default:
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MIPS_INVAL("Compact branch/jump");
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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}
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if (bcond_compute == 0) {
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/* Uncoditional compact branch */
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switch (opc) {
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case OPC_BC:
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gen_goto_tb(ctx, 0, ctx->btarget);
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break;
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default:
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MIPS_INVAL("Compact branch/jump");
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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}
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} else {
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/* Conditional compact branch */
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TCGLabel *fs = gen_new_label();
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switch (opc) {
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case OPC_BGEUC:
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if (rs == 0 && rt != 0) {
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/* OPC_BLEZALC */
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BGEZALC */
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
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} else {
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/* OPC_BGEUC */
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
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}
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break;
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case OPC_BLTUC:
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if (rs == 0 && rt != 0) {
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/* OPC_BGTZALC */
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BLTZALC */
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
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} else {
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/* OPC_BLTUC */
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
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}
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break;
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case OPC_BGEC:
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if (rs == 0 && rt != 0) {
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/* OPC_BLEZC */
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BGEZC */
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
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} else {
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/* OPC_BGEC */
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
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}
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break;
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case OPC_BLTC:
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if (rs == 0 && rt != 0) {
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/* OPC_BGTZC */
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BLTZC */
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
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} else {
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/* OPC_BLTC */
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
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}
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break;
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case OPC_BEQZC:
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
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break;
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default:
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MIPS_INVAL("Compact conditional branch/jump");
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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}
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/* Generating branch here as compact branches don't have delay slot */
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gen_goto_tb(ctx, 1, ctx->btarget);
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gen_set_label(fs);
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gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
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}
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out:
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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/* nanoMIPS CP1 Branches */
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static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op,
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int32_t ft, int32_t offset)
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{
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target_ulong btarget;
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TCGv_i64 t0 = tcg_temp_new_i64();
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gen_load_fpr64(ctx, t0, ft);
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tcg_gen_andi_i64(t0, t0, 1);
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btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
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switch (op) {
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case NM_BC1EQZC:
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tcg_gen_xori_i64(t0, t0, 1);
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ctx->hflags |= MIPS_HFLAG_BC;
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break;
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case NM_BC1NEZC:
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/* t0 already set */
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ctx->hflags |= MIPS_HFLAG_BC;
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break;
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default:
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MIPS_INVAL("cp1 cond branch");
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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}
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tcg_gen_trunc_i64_tl(bcond, t0);
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ctx->btarget = btarget;
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out:
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tcg_temp_free_i64(t0);
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}
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static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
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{
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@ -18276,16 +18591,129 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_MOVE_BALC:
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{
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TCGv t0 = tcg_temp_new();
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int32_t s = sextract32(ctx->opcode, 0, 1) << 21 |
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extract32(ctx->opcode, 1, 20) << 1;
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rd = (extract32(ctx->opcode, 24, 1)) == 0 ? 4 : 5;
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rt = decode_gpr_gpr4_zero(extract32(ctx->opcode, 25, 1) << 3 |
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extract32(ctx->opcode, 21, 3));
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gen_load_gpr(t0, rt);
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tcg_gen_mov_tl(cpu_gpr[rd], t0);
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gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s);
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tcg_temp_free(t0);
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}
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break;
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case NM_P_BAL:
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{
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int32_t s = sextract32(ctx->opcode, 0, 1) << 25 |
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extract32(ctx->opcode, 1, 24) << 1;
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if ((extract32(ctx->opcode, 25, 1)) == 0) {
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/* BC */
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gen_compute_branch_nm(ctx, OPC_BEQ, 4, 0, 0, s);
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} else {
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/* BALC */
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gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s);
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}
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}
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break;
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case NM_P_J:
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switch (extract32(ctx->opcode, 12, 4)) {
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case NM_JALRC:
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case NM_JALRC_HB:
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gen_compute_branch_nm(ctx, OPC_JALR, 4, rs, rt, 0);
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break;
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case NM_P_BALRSC:
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gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt);
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_P_BR1:
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{
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int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
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extract32(ctx->opcode, 1, 13) << 1;
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switch (extract32(ctx->opcode, 14, 2)) {
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case NM_BEQC:
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gen_compute_branch_nm(ctx, OPC_BEQ, 4, rs, rt, s);
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break;
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case NM_P_BR3A:
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s = sextract32(ctx->opcode, 0, 1) << 14 |
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extract32(ctx->opcode, 1, 13) << 1;
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check_cp1_enabled(ctx);
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switch (extract32(ctx->opcode, 16, 5)) {
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case NM_BC1EQZC:
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gen_compute_branch_cp1_nm(ctx, OPC_BC1EQZ, rt, s);
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break;
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case NM_BC1NEZC:
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gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_BGEC:
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if (rs == rt) {
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gen_compute_compact_branch_nm(ctx, OPC_BC, rs, rt, s);
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} else {
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gen_compute_compact_branch_nm(ctx, OPC_BGEC, rs, rt, s);
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}
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break;
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case NM_BGEUC:
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if (rs == rt || rt == 0) {
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gen_compute_compact_branch_nm(ctx, OPC_BC, 0, 0, s);
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} else if (rs == 0) {
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gen_compute_compact_branch_nm(ctx, OPC_BEQZC, rt, 0, s);
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} else {
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gen_compute_compact_branch_nm(ctx, OPC_BGEUC, rs, rt, s);
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}
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break;
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}
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}
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break;
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case NM_P_BR2:
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{
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int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
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extract32(ctx->opcode, 1, 13) << 1;
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switch (extract32(ctx->opcode, 14, 2)) {
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case NM_BNEC:
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gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
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break;
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case NM_BLTC:
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if (rs != 0 && rt != 0 && rs == rt) {
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/* NOP */
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ctx->hflags |= MIPS_HFLAG_FBNSLOT;
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} else {
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gen_compute_compact_branch_nm(ctx, OPC_BLTC, rs, rt, s);
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}
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break;
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case NM_BLTUC:
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if (rs == 0 || rs == rt) {
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/* NOP */
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ctx->hflags |= MIPS_HFLAG_FBNSLOT;
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} else {
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gen_compute_compact_branch_nm(ctx, OPC_BLTUC, rs, rt, s);
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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}
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break;
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case NM_P_BRI:
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||||
{
|
||||
int32_t s = sextract32(ctx->opcode, 0, 1) << 11 |
|
||||
extract32(ctx->opcode, 1, 10) << 1;
|
||||
uint32_t u = extract32(ctx->opcode, 11, 7);
|
||||
|
||||
gen_compute_imm_branch(ctx, extract32(ctx->opcode, 18, 3),
|
||||
rt, u, s);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
generate_exception_end(ctx, EXCP_RI);
|
||||
|
|
|
|||
Loading…
Reference in New Issue