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tcg/tci: Split out tci_args_rrrrrr

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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-29 22:16:05 -10:00
parent 1670a2b9bb
commit 120402b5cb
1 changed files with 20 additions and 11 deletions
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31
tcg/tci.c
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@ -260,6 +260,17 @@ static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
*r4 = tci_read_r(tb_ptr);
*c5 = tci_read_b(tb_ptr);
}
static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*r3 = tci_read_r(tb_ptr);
*r4 = tci_read_r(tb_ptr);
*r5 = tci_read_r(tb_ptr);
}
#endif
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
@ -422,7 +433,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
TCGReg r3, r4;
TCGReg r3, r4, r5;
uint64_t T1, T2;
#endif
TCGMemOpIdx oi;
@ -628,18 +639,16 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
tmp64 = tci_read_r64(regs, &tb_ptr);
tmp64 += tci_read_r64(regs, &tb_ptr);
tci_write_reg64(regs, t1, t0, tmp64);
tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 + T2);
break;
case INDEX_op_sub2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
tmp64 = tci_read_r64(regs, &tb_ptr);
tmp64 -= tci_read_r64(regs, &tb_ptr);
tci_write_reg64(regs, t1, t0, tmp64);
tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
case INDEX_op_brcond2_i32:
tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr);