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linux-user: Save the correct resume address for MIPS signal handling

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The current ISA mode needs to be saved in bit 0 of the resume address.
If the current instruction happens to be in a branch delay slot, then
the address of the preceding jump instruction should be stored instead.
exception_resume_pc already does both of these tasks, so it is
made available and reused.

MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the
first instruction of the signal handler as a delay slot instruction.

Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Kwok Cheung Yeung 2013-05-17 14:51:21 -07:00 committed by Aurelien Jarno
parent ea3164aafc
commit 1239b472bb
3 changed files with 5 additions and 3 deletions
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3
linux-user/signal.c
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@ -2528,7 +2528,8 @@ setup_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
int err = 0;
int i;
err |= __put_user(regs->active_tc.PC, &sc->sc_pc);
err |= __put_user(exception_resume_pc(regs), &sc->sc_pc);
regs->hflags &= ~MIPS_HFLAG_BMASK;
__put_user(0, &sc->sc_regs[0]);
for (i = 1; i < 32; ++i) {

1
target-mips/cpu.h
View File

@ -668,6 +668,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
int rw);
#endif
target_ulong exception_resume_pc (CPUMIPSState *env);
static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)

4
target-mips/helper.c
View File

@ -366,8 +366,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_CACHE] = "cache error",
};
#if !defined(CONFIG_USER_ONLY)
static target_ulong exception_resume_pc (CPUMIPSState *env)
target_ulong exception_resume_pc (CPUMIPSState *env)
{
target_ulong bad_pc;
target_ulong isa_mode;
@ -383,6 +382,7 @@ static target_ulong exception_resume_pc (CPUMIPSState *env)
return bad_pc;
}
#if !defined(CONFIG_USER_ONLY)
static void set_hflags_for_handler (CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */