target/arm: Mark up sysregs for HFGITR bits 12..17
Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 12..17. These bits cover AT address translation instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org
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@ -660,6 +660,12 @@ typedef enum FGTBit {
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DO_BIT(HFGITR, DCCVADP),
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DO_BIT(HFGITR, DCCIVAC),
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DO_BIT(HFGITR, DCZVA),
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DO_BIT(HFGITR, ATS1E1R),
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DO_BIT(HFGITR, ATS1E1W),
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DO_BIT(HFGITR, ATS1E0R),
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DO_BIT(HFGITR, ATS1E0W),
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DO_BIT(HFGITR, ATS1E1RP),
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DO_BIT(HFGITR, ATS1E1WP),
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} FGTBit;
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#undef DO_BIT
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@ -5400,18 +5400,22 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
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.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
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.fgt = FGT_ATS1E1R,
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.writefn = ats_write64 },
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{ .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
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.fgt = FGT_ATS1E1W,
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.writefn = ats_write64 },
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{ .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
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.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
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.fgt = FGT_ATS1E0R,
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.writefn = ats_write64 },
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{ .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
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.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
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.fgt = FGT_ATS1E0W,
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.writefn = ats_write64 },
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{ .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
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@ -7880,10 +7884,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
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{ .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
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.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
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.fgt = FGT_ATS1E1RP,
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.writefn = ats_write64 },
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{ .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
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.fgt = FGT_ATS1E1WP,
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.writefn = ats_write64 },
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};
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