OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

mips: Add support for VInt and VEIC irq modes 

Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
This commit is contained in:
Edgar E. Iglesias 2010-08-06 12:21:16 +02:00 committed by Edgar E. Iglesias
parent d087bb3e38
commit 138afb024b
3 changed files with 51 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
cpu-exec.c
View File

@ -448,7 +448,7 @@ int cpu_exec(CPUState *env1)
}
#elif defined(TARGET_MIPS)
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
(env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
cpu_mips_hw_interrupts_pending(env) &&
(env->CP0_Status & (1 << CP0St_IE)) &&
!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&

23
target-mips/cpu.h
View File

@ -525,6 +525,29 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
env->active_tc.gpr[2] = 0;
}
static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
{
int32_t pending;
int32_t status;
int r;
pending = env->CP0_Cause & CP0Ca_IP_mask;
status = env->CP0_Status & CP0Ca_IP_mask;
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
/* A MIPS configured with a vectorizing external interrupt controller
will feed a vector into the Cause pending lines. The core treats
the status lines as a vector level, not as indiviual masks. */
r = pending > status;
} else {
/* A MIPS configured with compatibility or VInt (Vectored Interrupts)
treats the pending lines as individual interrupt lines, the status
lines are individual masks. */
r = pending & status;
}
return r;
}
#include "cpu-all.h"
/* Memory access type :

27
target-mips/helper.c
View File

@ -478,6 +478,33 @@ void do_interrupt (CPUState *env)
cause = 0;
if (env->CP0_Cause & (1 << CP0Ca_IV))
offset = 0x200;
if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
/* Vectored Interrupts. */
unsigned int spacing;
unsigned int vector;
unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
/* Compute the Vector Spacing. */
spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
spacing <<= 5;
if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
/* For VInt mode, the MIPS computes the vector internally. */
for (vector = 0; vector < 8; vector++) {
if (pending & 1) {
/* Found it. */
break;
}
pending >>= 1;
}
} else {
/* For VEIC mode, the external interrupt controller feeds the
vector throught the CP0Cause IP lines. */
vector = pending;
}
offset = 0x200 + vector * spacing;
}
goto set_EPC;
case EXCP_LTLBL:
cause = 1;