target/ppc: do not reset reserve_addr in exec_enter
In case when atomic operation is not supported, exit_atomic is called and we stop the world and execute the atomic operation. This results in a following call chain: tcg_gen_atomic_cmpxchg_tl() -> gen_helper_exit_atomic() -> HELPER(exit_atomic) -> cpu_loop_exit_atomic() -> EXCP_ATOMIC -> qemu_tcg_cpu_thread_fn() => case EXCP_ATOMIC -> cpu_exec_step_atomic() -> cpu_step_atomic() -> cc->cpu_exec_enter() = ppc_cpu_exec_enter() Sets env->reserve_addr = -1; But by the time it return back, the reservation is erased and the code fails, this continues forever and the lock is never taken. Instead set this in powerpc_excp() Now that ppc_cpu_exec_enter() doesn't have anything meaningful to do, let us get rid of the function. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -728,6 +728,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
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cs->exception_index = POWERPC_EXCP_NONE;
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env->error_code = 0;
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/* Reset the reservation */
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env->reserve_addr = -1;
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/* Any interrupt is context synchronizing, check if TCG TLB
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* needs a delayed flush on ppc64
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*/
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@ -10436,14 +10436,6 @@ static bool ppc_cpu_has_work(CPUState *cs)
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return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
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}
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static void ppc_cpu_exec_enter(CPUState *cs)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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env->reserve_addr = -1;
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}
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/* CPUClass::reset() */
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static void ppc_cpu_reset(CPUState *s)
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{
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@ -10660,7 +10652,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
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cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
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cc->vmsd = &vmstate_ppc_cpu;
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#endif
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cc->cpu_exec_enter = ppc_cpu_exec_enter;
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#if defined(CONFIG_SOFTMMU)
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cc->write_elf64_note = ppc64_cpu_write_elf64_note;
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cc->write_elf32_note = ppc32_cpu_write_elf32_note;
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