s390x/tcg: Implement VECTOR STRING RANGE COMPARE
Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
This commit is contained in:
David Hildenbrand
parent
be6324c6b7
commit
13b0228f77
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@ -236,6 +236,18 @@ DEF_HELPER_FLAGS_3(gvec_vistr32, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
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DEF_HELPER_4(gvec_vistr_cc8, void, ptr, cptr, env, i32)
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DEF_HELPER_4(gvec_vistr_cc16, void, ptr, cptr, env, i32)
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DEF_HELPER_4(gvec_vistr_cc32, void, ptr, cptr, env, i32)
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DEF_HELPER_FLAGS_5(gvec_vstrc8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vstrc16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vstrc32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vstrc_rt8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vstrc_rt16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vstrc_rt32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_6(gvec_vstrc_cc8, void, ptr, cptr, cptr, cptr, env, i32)
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DEF_HELPER_6(gvec_vstrc_cc16, void, ptr, cptr, cptr, cptr, env, i32)
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DEF_HELPER_6(gvec_vstrc_cc32, void, ptr, cptr, cptr, cptr, env, i32)
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DEF_HELPER_6(gvec_vstrc_cc_rt8, void, ptr, cptr, cptr, cptr, env, i32)
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DEF_HELPER_6(gvec_vstrc_cc_rt16, void, ptr, cptr, cptr, cptr, env, i32)
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DEF_HELPER_6(gvec_vstrc_cc_rt32, void, ptr, cptr, cptr, cptr, env, i32)
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_3(servc, i32, env, i64, i64)
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@ -1201,6 +1201,8 @@
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F(0xe781, VFENE, VRR_b, V, 0, 0, 0, 0, vfene, 0, IF_VEC)
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/* VECTOR ISOLATE STRING */
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F(0xe75c, VISTR, VRR_a, V, 0, 0, 0, 0, vistr, 0, IF_VEC)
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/* VECTOR STRING RANGE COMPARE */
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F(0xe78a, VSTRC, VRR_d, V, 0, 0, 0, 0, vstrc, 0, IF_VEC)
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#ifndef CONFIG_USER_ONLY
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/* COMPARE AND SWAP AND PURGE */
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@ -217,6 +217,10 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
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tcg_gen_gvec_4_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
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16, 16, data, fn)
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#define gen_gvec_4_ptr(v1, v2, v3, v4, ptr, data, fn) \
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tcg_gen_gvec_4_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
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ptr, 16, 16, data, fn)
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#define gen_gvec_dup_i64(es, v1, c) \
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tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c)
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#define gen_gvec_mov(v1, v2) \
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@ -2479,3 +2483,58 @@ static DisasJumpType op_vistr(DisasContext *s, DisasOps *o)
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}
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return DISAS_NEXT;
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}
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static DisasJumpType op_vstrc(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = get_field(s->fields, m5);
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const uint8_t m6 = get_field(s->fields, m6);
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static gen_helper_gvec_4 * const g[3] = {
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gen_helper_gvec_vstrc8,
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gen_helper_gvec_vstrc16,
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gen_helper_gvec_vstrc32,
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};
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static gen_helper_gvec_4 * const g_rt[3] = {
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gen_helper_gvec_vstrc_rt8,
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gen_helper_gvec_vstrc_rt16,
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gen_helper_gvec_vstrc_rt32,
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};
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static gen_helper_gvec_4_ptr * const g_cc[3] = {
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gen_helper_gvec_vstrc_cc8,
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gen_helper_gvec_vstrc_cc16,
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gen_helper_gvec_vstrc_cc32,
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};
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static gen_helper_gvec_4_ptr * const g_cc_rt[3] = {
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gen_helper_gvec_vstrc_cc_rt8,
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gen_helper_gvec_vstrc_cc_rt16,
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gen_helper_gvec_vstrc_cc_rt32,
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};
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if (es > ES_32) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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if (extract32(m6, 0, 1)) {
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if (extract32(m6, 2, 1)) {
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gen_gvec_4_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
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get_field(s->fields, v3), get_field(s->fields, v4),
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cpu_env, m6, g_cc_rt[es]);
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} else {
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gen_gvec_4_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
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get_field(s->fields, v3), get_field(s->fields, v4),
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cpu_env, m6, g_cc[es]);
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}
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set_cc_static(s);
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} else {
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if (extract32(m6, 2, 1)) {
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gen_gvec_4_ool(get_field(s->fields, v1), get_field(s->fields, v2),
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get_field(s->fields, v3), get_field(s->fields, v4),
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m6, g_rt[es]);
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} else {
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gen_gvec_4_ool(get_field(s->fields, v1), get_field(s->fields, v2),
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get_field(s->fields, v3), get_field(s->fields, v4),
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m6, g[es]);
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}
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}
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return DISAS_NEXT;
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}
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@ -117,4 +117,25 @@ static inline void s390_vec_write_element64(S390Vector *v, uint8_t enr,
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v->doubleword[enr] = data;
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}
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static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,
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uint8_t es, uint64_t data)
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{
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switch (es) {
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case MO_8:
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s390_vec_write_element8(v, enr, data);
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break;
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case MO_16:
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s390_vec_write_element16(v, enr, data);
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break;
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case MO_32:
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s390_vec_write_element32(v, enr, data);
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break;
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case MO_64:
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s390_vec_write_element64(v, enr, data);
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break;
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default:
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g_assert_not_reached();
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}
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}
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#endif /* S390X_VEC_H */
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@ -328,3 +328,146 @@ void HELPER(gvec_vistr_cc##BITS)(void *v1, const void *v2, CPUS390XState *env, \
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DEF_VISTR_CC_HELPER(8)
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DEF_VISTR_CC_HELPER(16)
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DEF_VISTR_CC_HELPER(32)
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static bool element_compare(uint32_t data, uint32_t l, uint8_t c)
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{
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const bool equal = extract32(c, 7, 1);
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const bool lower = extract32(c, 6, 1);
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const bool higher = extract32(c, 5, 1);
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if (data < l) {
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return lower;
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} else if (data > l) {
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return higher;
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}
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return equal;
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}
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static int vstrc(void *v1, const void *v2, const void *v3, const void *v4,
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bool in, bool rt, bool zs, uint8_t es)
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{
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const uint64_t mask = get_element_lsbs_mask(es);
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uint64_t a0 = s390_vec_read_element64(v2, 0);
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uint64_t a1 = s390_vec_read_element64(v2, 1);
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int first_zero = 16, first_match = 16;
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S390Vector rt_result = {};
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uint64_t z0, z1;
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int i, j;
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if (zs) {
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z0 = zero_search(a0, mask);
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z1 = zero_search(a1, mask);
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first_zero = match_index(z0, z1);
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}
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for (i = 0; i < 16 / (1 << es); i++) {
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const uint32_t data = s390_vec_read_element(v2, i, es);
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const int cur_byte = i * (1 << es);
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bool any_match = false;
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/* if we don't need a bit vector, we can stop early */
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if (cur_byte == first_zero && !rt) {
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break;
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}
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for (j = 0; j < 16 / (1 << es); j += 2) {
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const uint32_t l1 = s390_vec_read_element(v3, j, es);
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const uint32_t l2 = s390_vec_read_element(v3, j + 1, es);
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/* we are only interested in the highest byte of each element */
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const uint8_t c1 = s390_vec_read_element8(v4, j * (1 << es));
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const uint8_t c2 = s390_vec_read_element8(v4, (j + 1) * (1 << es));
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if (element_compare(data, l1, c1) &&
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element_compare(data, l2, c2)) {
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any_match = true;
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break;
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}
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}
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/* invert the result if requested */
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any_match = in ^ any_match;
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if (any_match) {
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/* indicate bit vector if requested */
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if (rt) {
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const uint64_t val = -1ull;
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first_match = MIN(cur_byte, first_match);
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s390_vec_write_element(&rt_result, i, es, val);
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} else {
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/* stop on the first match */
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first_match = cur_byte;
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break;
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}
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}
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}
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if (rt) {
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*(S390Vector *)v1 = rt_result;
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} else {
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s390_vec_write_element64(v1, 0, MIN(first_match, first_zero));
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s390_vec_write_element64(v1, 1, 0);
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}
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if (first_zero == 16 && first_match == 16) {
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return 3; /* no match */
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} else if (first_zero == 16) {
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return 1; /* matching elements, no match for zero */
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} else if (first_match < first_zero) {
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return 2; /* matching elements before match for zero */
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}
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return 0; /* match for zero */
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}
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#define DEF_VSTRC_HELPER(BITS) \
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void HELPER(gvec_vstrc##BITS)(void *v1, const void *v2, const void *v3, \
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const void *v4, uint32_t desc) \
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{ \
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const bool in = extract32(simd_data(desc), 3, 1); \
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const bool zs = extract32(simd_data(desc), 1, 1); \
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\
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vstrc(v1, v2, v3, v4, in, 0, zs, MO_##BITS); \
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}
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DEF_VSTRC_HELPER(8)
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DEF_VSTRC_HELPER(16)
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DEF_VSTRC_HELPER(32)
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#define DEF_VSTRC_RT_HELPER(BITS) \
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void HELPER(gvec_vstrc_rt##BITS)(void *v1, const void *v2, const void *v3, \
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const void *v4, uint32_t desc) \
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{ \
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const bool in = extract32(simd_data(desc), 3, 1); \
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const bool zs = extract32(simd_data(desc), 1, 1); \
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\
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vstrc(v1, v2, v3, v4, in, 1, zs, MO_##BITS); \
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}
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DEF_VSTRC_RT_HELPER(8)
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DEF_VSTRC_RT_HELPER(16)
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DEF_VSTRC_RT_HELPER(32)
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#define DEF_VSTRC_CC_HELPER(BITS) \
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void HELPER(gvec_vstrc_cc##BITS)(void *v1, const void *v2, const void *v3, \
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const void *v4, CPUS390XState *env, \
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uint32_t desc) \
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{ \
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const bool in = extract32(simd_data(desc), 3, 1); \
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const bool zs = extract32(simd_data(desc), 1, 1); \
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\
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env->cc_op = vstrc(v1, v2, v3, v4, in, 0, zs, MO_##BITS); \
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}
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DEF_VSTRC_CC_HELPER(8)
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DEF_VSTRC_CC_HELPER(16)
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DEF_VSTRC_CC_HELPER(32)
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#define DEF_VSTRC_CC_RT_HELPER(BITS) \
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void HELPER(gvec_vstrc_cc_rt##BITS)(void *v1, const void *v2, const void *v3, \
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const void *v4, CPUS390XState *env, \
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uint32_t desc) \
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{ \
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const bool in = extract32(simd_data(desc), 3, 1); \
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const bool zs = extract32(simd_data(desc), 1, 1); \
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\
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env->cc_op = vstrc(v1, v2, v3, v4, in, 1, zs, MO_##BITS); \
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}
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DEF_VSTRC_CC_RT_HELPER(8)
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DEF_VSTRC_CC_RT_HELPER(16)
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DEF_VSTRC_CC_RT_HELPER(32)
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