PPC: e500: Merge 32 and 64 bit SPE emulation

Today we have a lot of conditional code in the SPE emulation depending on
whether we have 64bit GPRs or not.

Unfortunately the assumption that we can just recycle the 64bit GPR
implementation is wrong. Normal SPE implementations maintain the upper 32 bits
on all non-SPE instructions which then only modify the low 32 bits. However
all instructions we model that adhere to the normal SF based switching don't
care whether they operate on 32 or 64 bit registers and just always use the full
64 bits.

So let's remove that dubious SPE optimization and revert everything to the same
code path the 32bit target code was taking. That way we get rid of differences
between the two implementations, but will get a slight performance hit when
emulating SPE instructions.

This fixes SPE emulation with qemu-system-ppc64 for me.

Signed-off-by: Alexander Graf <agraf@suse.de>

target-ppc/cpu.h

@@ -908,10 +908,8 @@ struct CPUPPCState {
      */
     /* general purpose registers */
     target_ulong gpr[32];
-#if !defined(TARGET_PPC64)
     /* Storage for GPR MSB, used by the SPE extension */
     target_ulong gprh[32];
-#endif
     /* LR */
     target_ulong lr;
     /* CTR */
@@ -1164,7 +1162,6 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
     uint64_t gprv;
 
     gprv = env->gpr[gprn];
-#if !defined(TARGET_PPC64)
     if (env->flags & POWERPC_FLAG_SPE) {
         /* If the CPU implements the SPE extension, we have to get the
          * high bits of the GPR from the gprh storage area
@@ -1172,7 +1169,6 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
         gprv &= 0xFFFFFFFFULL;
         gprv |= (uint64_t)env->gprh[gprn] << 32;
     }
-#endif
 
     return gprv;
 }