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target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns

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All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-01-18 09:45:08 +08:00 committed by Alistair Francis
parent aaae69942f
commit 13dbc826fd
1 changed files with 25 additions and 2 deletions
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27
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2123,8 +2123,31 @@ GEN_OPIVX_TRANS(vasub_vx, opivx_check)
GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
{
/*
* All Zve* extensions support all vector fixed-point arithmetic
* instructions, except that vsmul.vv and vsmul.vx are not supported
* for EEW=64 in Zve64*. (Section 18.2)
*/
return opivv_check(s, a) &&
(!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
}
static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
{
/*
* All Zve* extensions support all vector fixed-point arithmetic
* instructions, except that vsmul.vv and vsmul.vx are not supported
* for EEW=64 in Zve64*. (Section 18.2)
*/
return opivx_check(s, a) &&
(!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
}
GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
GEN_OPIVX_TRANS(vsmul_vx, vsmul_vx_check)
/* Vector Single-Width Scaling Shift Instructions */
GEN_OPIVV_TRANS(vssrl_vv, opivv_check)