target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
All Zve* extensions support all vector fixed-point arithmetic instructions, except that vsmul.vv and vsmul.vx are not supported for EEW=64 in Zve64*. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -2123,8 +2123,31 @@ GEN_OPIVX_TRANS(vasub_vx, opivx_check)
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GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
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GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
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/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
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/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
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GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
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GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
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static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
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{
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/*
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* All Zve* extensions support all vector fixed-point arithmetic
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* instructions, except that vsmul.vv and vsmul.vx are not supported
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* for EEW=64 in Zve64*. (Section 18.2)
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*/
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return opivv_check(s, a) &&
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(!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
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}
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static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
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{
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/*
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* All Zve* extensions support all vector fixed-point arithmetic
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* instructions, except that vsmul.vv and vsmul.vx are not supported
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* for EEW=64 in Zve64*. (Section 18.2)
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*/
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return opivx_check(s, a) &&
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(!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
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}
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GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
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GEN_OPIVX_TRANS(vsmul_vx, vsmul_vx_check)
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/* Vector Single-Width Scaling Shift Instructions */
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/* Vector Single-Width Scaling Shift Instructions */
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GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
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GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
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