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target/arm: Introduce aarch64_pstate_valid_mask 

Use this along the exception return path, where we previously
accepted any values.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200208125816.14954-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-08 12:58:06 +00:00 committed by Peter Maydell
parent 70dae0d069
commit 1408451118
2 changed files with 13 additions and 0 deletions
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1
target/arm/helper-a64.c
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@ -1032,6 +1032,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
cur_el, new_el, env->regs[15]);
} else {
env->aarch64 = 1;
spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar);
pstate_write(env, spsr);
if (!arm_singlestep_active(env)) {
env->pstate &= ~PSTATE_SS;

12
target/arm/internals.h
View File

@ -1085,6 +1085,18 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
return valid;
}
static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
{
uint32_t valid;
valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV;
if (isar_feature_aa64_bti(id)) {
valid |= PSTATE_BTYPE;
}
return valid;
}
/*
* Parameters of a given virtual address, as extracted from the
* translation control register (TCR) for a given regime.