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hw/block/nvme: Add support for Namespace Types 

Define the structures and constants required to implement
Namespace Types support.

Namespace Types introduce a new command set, "I/O Command Sets",
that allows the host to retrieve the command sets associated with
a namespace. Introduce support for the command set and enable
detection for the NVM Command Set.

The new workflows for identify commands rely heavily on zero-filled
identify structs. E.g., certain CNS commands are defined to return
a zero-filled identify struct when an inactive namespace NSID
is supplied.

Add a helper function in order to avoid code duplication when
reporting zero-filled identify structures.

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Signed-off-by: Dmitry Fomichev <dmitry.fomichev@wdc.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
This commit is contained in:
Niklas Cassel 2020-12-09 05:04:03 +09:00 committed by Klaus Jensen
parent 62e8faa468
commit 141354d55b
5 changed files with 217 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/block/nvme-ns.c
View File

@ -43,6 +43,8 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp)
id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(ns)); id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(ns));
ns->csi = NVME_CSI_NVM;
/* no thin provisioning */ /* no thin provisioning */
id_ns->ncap = id_ns->nsze; id_ns->ncap = id_ns->nsze;
id_ns->nuse = id_ns->ncap; id_ns->nuse = id_ns->ncap;

1
hw/block/nvme-ns.h
View File

@ -31,6 +31,7 @@ typedef struct NvmeNamespace {
int64_t size; int64_t size;
NvmeIdNs id_ns; NvmeIdNs id_ns;
const uint32_t *iocs; const uint32_t *iocs;
uint8_t csi;
NvmeNamespaceParams params; NvmeNamespaceParams params;

188
hw/block/nvme.c
View File

@ -1596,7 +1596,7 @@ static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
DMA_DIRECTION_FROM_DEVICE, req); DMA_DIRECTION_FROM_DEVICE, req);
} }
static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint32_t buf_len, static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8_t csi, uint32_t buf_len,
uint64_t off, NvmeRequest *req) uint64_t off, NvmeRequest *req)
{ {
NvmeEffectsLog log = {}; NvmeEffectsLog log = {};
@ -1611,8 +1611,15 @@ static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint32_t buf_len,
switch (NVME_CC_CSS(n->bar.cc)) { switch (NVME_CC_CSS(n->bar.cc)) {
case NVME_CC_CSS_NVM: case NVME_CC_CSS_NVM:
src_iocs = nvme_cse_iocs_nvm; src_iocs = nvme_cse_iocs_nvm;
/* fall through */
case NVME_CC_CSS_ADMIN_ONLY: case NVME_CC_CSS_ADMIN_ONLY:
break; break;
case NVME_CC_CSS_CSI:
switch (csi) {
case NVME_CSI_NVM:
src_iocs = nvme_cse_iocs_nvm;
break;
}
} }
memcpy(log.acs, nvme_cse_acs, sizeof(nvme_cse_acs)); memcpy(log.acs, nvme_cse_acs, sizeof(nvme_cse_acs));
@ -1638,6 +1645,7 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
uint8_t lid = dw10 & 0xff; uint8_t lid = dw10 & 0xff;
uint8_t lsp = (dw10 >> 8) & 0xf; uint8_t lsp = (dw10 >> 8) & 0xf;
uint8_t rae = (dw10 >> 15) & 0x1; uint8_t rae = (dw10 >> 15) & 0x1;
uint8_t csi = le32_to_cpu(cmd->cdw14) >> 24;
uint32_t numdl, numdu; uint32_t numdl, numdu;
uint64_t off, lpol, lpou; uint64_t off, lpol, lpou;
size_t len; size_t len;
@ -1671,7 +1679,7 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
case NVME_LOG_FW_SLOT_INFO: case NVME_LOG_FW_SLOT_INFO:
return nvme_fw_log_info(n, len, off, req); return nvme_fw_log_info(n, len, off, req);
case NVME_LOG_CMD_EFFECTS: case NVME_LOG_CMD_EFFECTS:
return nvme_cmd_effects(n, len, off, req); return nvme_cmd_effects(n, csi, len, off, req);
default: default:
trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid); trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid);
return NVME_INVALID_FIELD | NVME_DNR; return NVME_INVALID_FIELD | NVME_DNR;
@ -1784,6 +1792,13 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req)
return NVME_SUCCESS; return NVME_SUCCESS;
} }
static uint16_t nvme_rpt_empty_id_struct(NvmeCtrl *n, NvmeRequest *req)
{
uint8_t id[NVME_IDENTIFY_DATA_SIZE] = {};
return nvme_dma(n, id, sizeof(id), DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req) static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req)
{ {
trace_pci_nvme_identify_ctrl(); trace_pci_nvme_identify_ctrl();
@ -1792,11 +1807,23 @@ static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req)
DMA_DIRECTION_FROM_DEVICE, req); DMA_DIRECTION_FROM_DEVICE, req);
} }
static uint16_t nvme_identify_ctrl_csi(NvmeCtrl *n, NvmeRequest *req)
{
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
trace_pci_nvme_identify_ctrl_csi(c->csi);
if (c->csi == NVME_CSI_NVM) {
return nvme_rpt_empty_id_struct(n, req);
}
return NVME_INVALID_FIELD | NVME_DNR;
}
static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req) static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
{ {
NvmeNamespace *ns; NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)&req->cmd; NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
NvmeIdNs *id_ns, inactive = { 0 };
uint32_t nsid = le32_to_cpu(c->nsid); uint32_t nsid = le32_to_cpu(c->nsid);
trace_pci_nvme_identify_ns(nsid); trace_pci_nvme_identify_ns(nsid);
@ -1807,23 +1834,46 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
ns = nvme_ns(n, nsid); ns = nvme_ns(n, nsid);
if (unlikely(!ns)) { if (unlikely(!ns)) {
id_ns = &inactive; return nvme_rpt_empty_id_struct(n, req);
} else {
id_ns = &ns->id_ns;
} }
return nvme_dma(n, (uint8_t *)id_ns, sizeof(NvmeIdNs), return nvme_dma(n, (uint8_t *)&ns->id_ns, sizeof(NvmeIdNs),
DMA_DIRECTION_FROM_DEVICE, req); DMA_DIRECTION_FROM_DEVICE, req);
} }
static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req)
{
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint32_t nsid = le32_to_cpu(c->nsid);
trace_pci_nvme_identify_ns_csi(nsid, c->csi);
if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
return NVME_INVALID_NSID | NVME_DNR;
}
ns = nvme_ns(n, nsid);
if (unlikely(!ns)) {
return nvme_rpt_empty_id_struct(n, req);
}
if (c->csi == NVME_CSI_NVM) {
return nvme_rpt_empty_id_struct(n, req);
}
return NVME_INVALID_FIELD | NVME_DNR;
}
static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req) static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
{ {
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)&req->cmd; NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
static const int data_len = NVME_IDENTIFY_DATA_SIZE;
uint32_t min_nsid = le32_to_cpu(c->nsid); uint32_t min_nsid = le32_to_cpu(c->nsid);
uint32_t *list; uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {};
uint16_t ret; static const int data_len = sizeof(list);
int j = 0; uint32_t *list_ptr = (uint32_t *)list;
int i, j = 0;
trace_pci_nvme_identify_nslist(min_nsid); trace_pci_nvme_identify_nslist(min_nsid);
@ -1837,20 +1887,61 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
return NVME_INVALID_NSID | NVME_DNR; return NVME_INVALID_NSID | NVME_DNR;
} }
list = g_malloc0(data_len); for (i = 1; i <= n->num_namespaces; i++) {
for (int i = 1; i <= n->num_namespaces; i++) { ns = nvme_ns(n, i);
if (i <= min_nsid || !nvme_ns(n, i)) { if (!ns) {
continue; continue;
} }
list[j++] = cpu_to_le32(i); if (ns->params.nsid <= min_nsid) {
continue;
}
list_ptr[j++] = cpu_to_le32(ns->params.nsid);
if (j == data_len / sizeof(uint32_t)) { if (j == data_len / sizeof(uint32_t)) {
break; break;
} }
} }
ret = nvme_dma(n, (uint8_t *)list, data_len, DMA_DIRECTION_FROM_DEVICE,
req); return nvme_dma(n, list, data_len, DMA_DIRECTION_FROM_DEVICE, req);
g_free(list); }
return ret;
static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n, NvmeRequest *req)
{
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint32_t min_nsid = le32_to_cpu(c->nsid);
uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {};
static const int data_len = sizeof(list);
uint32_t *list_ptr = (uint32_t *)list;
int i, j = 0;
trace_pci_nvme_identify_nslist_csi(min_nsid, c->csi);
/*
* Same as in nvme_identify_nslist(), 0xffffffff/0xfffffffe are invalid.
*/
if (min_nsid >= NVME_NSID_BROADCAST - 1) {
return NVME_INVALID_NSID | NVME_DNR;
}
if (c->csi != NVME_CSI_NVM) {
return NVME_INVALID_FIELD | NVME_DNR;
}
for (i = 1; i <= n->num_namespaces; i++) {
ns = nvme_ns(n, i);
if (!ns) {
continue;
}
if (ns->params.nsid <= min_nsid) {
continue;
}
list_ptr[j++] = cpu_to_le32(ns->params.nsid);
if (j == data_len / sizeof(uint32_t)) {
break;
}
}
return nvme_dma(n, list, data_len, DMA_DIRECTION_FROM_DEVICE, req);
} }
static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req) static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
@ -1858,13 +1949,17 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
NvmeNamespace *ns; NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)&req->cmd; NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint32_t nsid = le32_to_cpu(c->nsid); uint32_t nsid = le32_to_cpu(c->nsid);
uint8_t list[NVME_IDENTIFY_DATA_SIZE]; uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {};
struct data { struct data {
struct { struct {
NvmeIdNsDescr hdr; NvmeIdNsDescr hdr;
uint8_t v[16]; uint8_t v[NVME_NIDL_UUID];
} uuid; } uuid;
struct {
NvmeIdNsDescr hdr;
uint8_t v;
} csi;
}; };
struct data *ns_descrs = (struct data *)list; struct data *ns_descrs = (struct data *)list;
@ -1880,19 +1975,31 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
return NVME_INVALID_FIELD | NVME_DNR; return NVME_INVALID_FIELD | NVME_DNR;
} }
memset(list, 0x0, sizeof(list));
/* /*
* Because the NGUID and EUI64 fields are 0 in the Identify Namespace data * Because the NGUID and EUI64 fields are 0 in the Identify Namespace data
* structure, a Namespace UUID (nidt = 0x3) must be reported in the * structure, a Namespace UUID (nidt = 0x3) must be reported in the
* Namespace Identification Descriptor. Add the namespace UUID here. * Namespace Identification Descriptor. Add the namespace UUID here.
*/ */
ns_descrs->uuid.hdr.nidt = NVME_NIDT_UUID; ns_descrs->uuid.hdr.nidt = NVME_NIDT_UUID;
ns_descrs->uuid.hdr.nidl = NVME_NIDT_UUID_LEN; ns_descrs->uuid.hdr.nidl = NVME_NIDL_UUID;
memcpy(&ns_descrs->uuid.v, ns->params.uuid.data, NVME_NIDT_UUID_LEN); memcpy(&ns_descrs->uuid.v, ns->params.uuid.data, NVME_NIDL_UUID);
return nvme_dma(n, list, NVME_IDENTIFY_DATA_SIZE, ns_descrs->csi.hdr.nidt = NVME_NIDT_CSI;
DMA_DIRECTION_FROM_DEVICE, req); ns_descrs->csi.hdr.nidl = NVME_NIDL_CSI;
ns_descrs->csi.v = ns->csi;
return nvme_dma(n, list, sizeof(list), DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_identify_cmd_set(NvmeCtrl *n, NvmeRequest *req)
{
uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {};
static const int data_len = sizeof(list);
trace_pci_nvme_identify_cmd_set();
NVME_SET_CSI(*list, NVME_CSI_NVM);
return nvme_dma(n, list, data_len, DMA_DIRECTION_FROM_DEVICE, req);
} }
static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req) static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req)
@ -1902,12 +2009,20 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req)
switch (le32_to_cpu(c->cns)) { switch (le32_to_cpu(c->cns)) {
case NVME_ID_CNS_NS: case NVME_ID_CNS_NS:
return nvme_identify_ns(n, req); return nvme_identify_ns(n, req);
case NVME_ID_CNS_CS_NS:
return nvme_identify_ns_csi(n, req);
case NVME_ID_CNS_CTRL: case NVME_ID_CNS_CTRL:
return nvme_identify_ctrl(n, req); return nvme_identify_ctrl(n, req);
case NVME_ID_CNS_CS_CTRL:
return nvme_identify_ctrl_csi(n, req);
case NVME_ID_CNS_NS_ACTIVE_LIST: case NVME_ID_CNS_NS_ACTIVE_LIST:
return nvme_identify_nslist(n, req); return nvme_identify_nslist(n, req);
case NVME_ID_CNS_CS_NS_ACTIVE_LIST:
return nvme_identify_nslist_csi(n, req);
case NVME_ID_CNS_NS_DESCR_LIST: case NVME_ID_CNS_NS_DESCR_LIST:
return nvme_identify_ns_descr_list(n, req); return nvme_identify_ns_descr_list(n, req);
case NVME_ID_CNS_IO_COMMAND_SET:
return nvme_identify_cmd_set(n, req);
default: default:
trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns));
return NVME_INVALID_FIELD | NVME_DNR; return NVME_INVALID_FIELD | NVME_DNR;
@ -2096,7 +2211,9 @@ defaults:
if (iv == n->admin_cq.vector) { if (iv == n->admin_cq.vector) {
result |= NVME_INTVC_NOCOALESCING; result |= NVME_INTVC_NOCOALESCING;
} }
break;
case NVME_COMMAND_SET_PROFILE:
result = 0;
break; break;
default: default:
result = nvme_feature_default[fid]; result = nvme_feature_default[fid];
@ -2258,6 +2375,12 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
break; break;
case NVME_TIMESTAMP: case NVME_TIMESTAMP:
return nvme_set_feature_timestamp(n, req); return nvme_set_feature_timestamp(n, req);
case NVME_COMMAND_SET_PROFILE:
if (dw11 & 0x1ff) {
trace_pci_nvme_err_invalid_iocsci(dw11 & 0x1ff);
return NVME_CMD_SET_CMB_REJECTED | NVME_DNR;
}
break;
default: default:
return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR; return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR;
} }
@ -2428,8 +2551,12 @@ static void nvme_select_ns_iocs(NvmeCtrl *n)
continue; continue;
} }
ns->iocs = nvme_cse_iocs_none; ns->iocs = nvme_cse_iocs_none;
if (NVME_CC_CSS(n->bar.cc) != NVME_CC_CSS_ADMIN_ONLY) { switch (ns->csi) {
ns->iocs = nvme_cse_iocs_nvm; case NVME_CSI_NVM:
if (NVME_CC_CSS(n->bar.cc) != NVME_CC_CSS_ADMIN_ONLY) {
ns->iocs = nvme_cse_iocs_nvm;
}
break;
} }
} }
} }
@ -3170,6 +3297,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
NVME_CAP_SET_CQR(n->bar.cap, 1); NVME_CAP_SET_CQR(n->bar.cap, 1);
NVME_CAP_SET_TO(n->bar.cap, 0xf); NVME_CAP_SET_TO(n->bar.cap, 0xf);
NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_NVM); NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_NVM);
NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_CSI_SUPP);
NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_ADMIN_ONLY); NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_ADMIN_ONLY);
NVME_CAP_SET_MPSMAX(n->bar.cap, 4); NVME_CAP_SET_MPSMAX(n->bar.cap, 4);

6
hw/block/trace-events
View File

@ -54,8 +54,12 @@ pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size,
pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16"" pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16""
pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=%"PRIu16"" pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=%"PRIu16""
pci_nvme_identify_ctrl(void) "identify controller" pci_nvme_identify_ctrl(void) "identify controller"
pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=0x%"PRIx8""
pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32""
pci_nvme_identify_ns_csi(uint32_t ns, uint8_t csi) "nsid=%"PRIu32", csi=0x%"PRIx8""
pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32""
pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi) "nsid=%"PRIu16", csi=0x%"PRIx8""
pci_nvme_identify_cmd_set(void) "identify i/o command set"
pci_nvme_identify_ns_descr_list(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_ns_descr_list(uint32_t ns) "nsid %"PRIu32""
pci_nvme_get_log(uint16_t cid, uint8_t lid, uint8_t lsp, uint8_t rae, uint32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" lsp 0x%"PRIx8" rae 0x%"PRIx8" len %"PRIu32" off %"PRIu64"" pci_nvme_get_log(uint16_t cid, uint8_t lid, uint8_t lsp, uint8_t rae, uint32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" lsp 0x%"PRIx8" rae 0x%"PRIx8" len %"PRIu32" off %"PRIu64""
pci_nvme_getfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t sel, uint32_t cdw11) "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" sel 0x%"PRIx8" cdw11 0x%"PRIx32"" pci_nvme_getfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t sel, uint32_t cdw11) "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" sel 0x%"PRIx8" cdw11 0x%"PRIx32""
@ -109,6 +113,7 @@ pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8""
pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8"" pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8""
pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64"" pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64""
pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size) "must be <= %"PRIu64", got %"PRIu64"" pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size) "must be <= %"PRIu64", got %"PRIu64""
pci_nvme_err_invalid_iocsci(uint32_t idx) "unsupported command set combination index %"PRIu32""
pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deletion, sid=%"PRIu16"" pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deletion, sid=%"PRIu16""
pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submission queue, invalid cqid=%"PRIu16"" pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submission queue, invalid cqid=%"PRIu16""
pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submission queue, invalid sqid=%"PRIu16"" pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submission queue, invalid sqid=%"PRIu16""
@ -165,6 +170,7 @@ pci_nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell write for
pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "completion queue doorbell write value beyond queue size, cqid=%"PRIu32", new_head=%"PRIu16", ignoring" pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "completion queue doorbell write value beyond queue size, cqid=%"PRIu32", new_head=%"PRIu16", ignoring"
pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write for nonexistent queue, sqid=%"PRIu32", ignoring" pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write for nonexistent queue, sqid=%"PRIu32", ignoring"
pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submission queue doorbell write value beyond queue size, sqid=%"PRIu32", new_head=%"PRIu16", ignoring" pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submission queue doorbell write value beyond queue size, sqid=%"PRIu32", new_head=%"PRIu16", ignoring"
pci_nvme_ub_unknown_css_value(void) "unknown value in cc.css field"
# xen-block.c # xen-block.c
xen_block_realize(const char *type, uint32_t disk, uint32_t partition) "%s d%up%u" xen_block_realize(const char *type, uint32_t disk, uint32_t partition) "%s d%up%u"

64
include/block/nvme.h
View File

@ -84,6 +84,7 @@ enum NvmeCapMask {
enum NvmeCapCss { enum NvmeCapCss {
NVME_CAP_CSS_NVM = 1 << 0, NVME_CAP_CSS_NVM = 1 << 0,
NVME_CAP_CSS_CSI_SUPP = 1 << 6,
NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, NVME_CAP_CSS_ADMIN_ONLY = 1 << 7,
}; };
@ -117,9 +118,25 @@ enum NvmeCcMask {
enum NvmeCcCss { enum NvmeCcCss {
NVME_CC_CSS_NVM = 0x0, NVME_CC_CSS_NVM = 0x0,
NVME_CC_CSS_CSI = 0x6,
NVME_CC_CSS_ADMIN_ONLY = 0x7, NVME_CC_CSS_ADMIN_ONLY = 0x7,
}; };
#define NVME_SET_CC_EN(cc, val) \
(cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT)
#define NVME_SET_CC_CSS(cc, val) \
(cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT)
#define NVME_SET_CC_MPS(cc, val) \
(cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT)
#define NVME_SET_CC_AMS(cc, val) \
(cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT)
#define NVME_SET_CC_SHN(cc, val) \
(cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT)
#define NVME_SET_CC_IOSQES(cc, val) \
(cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT)
#define NVME_SET_CC_IOCQES(cc, val) \
(cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT)
enum NvmeCstsShift { enum NvmeCstsShift {
CSTS_RDY_SHIFT = 0, CSTS_RDY_SHIFT = 0,
CSTS_CFS_SHIFT = 1, CSTS_CFS_SHIFT = 1,
@ -540,8 +557,13 @@ typedef struct QEMU_PACKED NvmeIdentify {
uint64_t rsvd2[2]; uint64_t rsvd2[2];
uint64_t prp1; uint64_t prp1;
uint64_t prp2; uint64_t prp2;
uint32_t cns; uint8_t cns;
uint32_t rsvd11[5]; uint8_t rsvd10;
uint16_t ctrlid;
uint16_t nvmsetid;
uint8_t rsvd11;
uint8_t csi;
uint32_t rsvd12[4];
} NvmeIdentify; } NvmeIdentify;
typedef struct QEMU_PACKED NvmeRwCmd { typedef struct QEMU_PACKED NvmeRwCmd {
@ -662,6 +684,7 @@ enum NvmeStatusCodes {
NVME_SGL_DESCR_TYPE_INVALID = 0x0011, NVME_SGL_DESCR_TYPE_INVALID = 0x0011,
NVME_INVALID_USE_OF_CMB = 0x0012, NVME_INVALID_USE_OF_CMB = 0x0012,
NVME_INVALID_PRP_OFFSET = 0x0013, NVME_INVALID_PRP_OFFSET = 0x0013,
NVME_CMD_SET_CMB_REJECTED = 0x002b,
NVME_LBA_RANGE = 0x0080, NVME_LBA_RANGE = 0x0080,
NVME_CAP_EXCEEDED = 0x0081, NVME_CAP_EXCEEDED = 0x0081,
NVME_NS_NOT_READY = 0x0082, NVME_NS_NOT_READY = 0x0082,
@ -789,11 +812,15 @@ typedef struct QEMU_PACKED NvmePSD {
#define NVME_IDENTIFY_DATA_SIZE 4096 #define NVME_IDENTIFY_DATA_SIZE 4096
enum { enum NvmeIdCns {
NVME_ID_CNS_NS = 0x0, NVME_ID_CNS_NS = 0x00,
NVME_ID_CNS_CTRL = 0x1, NVME_ID_CNS_CTRL = 0x01,
NVME_ID_CNS_NS_ACTIVE_LIST = 0x2, NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
NVME_ID_CNS_NS_DESCR_LIST = 0x3, NVME_ID_CNS_NS_DESCR_LIST = 0x03,
NVME_ID_CNS_CS_NS = 0x05,
NVME_ID_CNS_CS_CTRL = 0x06,
NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07,
NVME_ID_CNS_IO_COMMAND_SET = 0x1c,
}; };
typedef struct QEMU_PACKED NvmeIdCtrl { typedef struct QEMU_PACKED NvmeIdCtrl {
@ -944,6 +971,7 @@ enum NvmeFeatureIds {
NVME_WRITE_ATOMICITY = 0xa, NVME_WRITE_ATOMICITY = 0xa,
NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, NVME_ASYNCHRONOUS_EVENT_CONF = 0xb,
NVME_TIMESTAMP = 0xe, NVME_TIMESTAMP = 0xe,
NVME_COMMAND_SET_PROFILE = 0x19,
NVME_SOFTWARE_PROGRESS_MARKER = 0x80, NVME_SOFTWARE_PROGRESS_MARKER = 0x80,
NVME_FID_MAX = 0x100, NVME_FID_MAX = 0x100,
}; };
@ -1033,18 +1061,26 @@ typedef struct QEMU_PACKED NvmeIdNsDescr {
uint8_t rsvd2[2]; uint8_t rsvd2[2];
} NvmeIdNsDescr; } NvmeIdNsDescr;
enum { enum NvmeNsIdentifierLength {
NVME_NIDT_EUI64_LEN = 8, NVME_NIDL_EUI64 = 8,
NVME_NIDT_NGUID_LEN = 16, NVME_NIDL_NGUID = 16,
NVME_NIDT_UUID_LEN = 16, NVME_NIDL_UUID = 16,
NVME_NIDL_CSI = 1,
}; };
enum NvmeNsIdentifierType { enum NvmeNsIdentifierType {
NVME_NIDT_EUI64 = 0x1, NVME_NIDT_EUI64 = 0x01,
NVME_NIDT_NGUID = 0x2, NVME_NIDT_NGUID = 0x02,
NVME_NIDT_UUID = 0x3, NVME_NIDT_UUID = 0x03,
NVME_NIDT_CSI = 0x04,
}; };
enum NvmeCsi {
NVME_CSI_NVM = 0x00,
};
#define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi)))
/*Deallocate Logical Block Features*/ /*Deallocate Logical Block Features*/
#define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10)
#define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08)