hw/arm/digic: add UART support
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-5-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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142593c9d7
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@ -24,6 +24,8 @@
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#define DIGIC4_TIMER_BASE(n) (0xc0210000 + (n) * 0x100)
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#define DIGIC4_TIMER_BASE(n) (0xc0210000 + (n) * 0x100)
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#define DIGIC_UART_BASE 0xc0800000
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static void digic_init(Object *obj)
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static void digic_init(Object *obj)
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{
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{
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DigicState *s = DIGIC(obj);
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DigicState *s = DIGIC(obj);
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@ -43,6 +45,11 @@ static void digic_init(Object *obj)
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snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
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snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
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object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL);
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object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL);
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}
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}
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object_initialize(&s->uart, sizeof(s->uart), TYPE_DIGIC_UART);
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dev = DEVICE(&s->uart);
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qdev_set_parent_bus(dev, sysbus_get_default());
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object_property_add_child(obj, "uart", OBJECT(&s->uart), NULL);
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}
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}
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static void digic_realize(DeviceState *dev, Error **errp)
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static void digic_realize(DeviceState *dev, Error **errp)
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@ -74,6 +81,15 @@ static void digic_realize(DeviceState *dev, Error **errp)
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sbd = SYS_BUS_DEVICE(&s->timer[i]);
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sbd = SYS_BUS_DEVICE(&s->timer[i]);
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sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
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sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
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}
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}
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object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sbd = SYS_BUS_DEVICE(&s->uart);
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sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE);
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}
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}
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static void digic_class_init(ObjectClass *oc, void *data)
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static void digic_class_init(ObjectClass *oc, void *data)
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@ -14,6 +14,7 @@ obj-$(CONFIG_COLDFIRE) += mcf_uart.o
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obj-$(CONFIG_OMAP) += omap_uart.o
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obj-$(CONFIG_OMAP) += omap_uart.o
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obj-$(CONFIG_SH4) += sh_serial.o
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obj-$(CONFIG_SH4) += sh_serial.o
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obj-$(CONFIG_PSERIES) += spapr_vty.o
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obj-$(CONFIG_PSERIES) += spapr_vty.o
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obj-$(CONFIG_DIGIC) += digic-uart.o
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common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
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common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
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common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
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common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
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@ -0,0 +1,195 @@
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/*
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* QEMU model of the Canon DIGIC UART block.
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*
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* Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This model is based on reverse engineering efforts
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* made by CHDK (http://chdk.wikia.com) and
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* Magic Lantern (http://www.magiclantern.fm) projects
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* contributors.
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*
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* See "Serial terminal" docs here:
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* http://magiclantern.wikia.com/wiki/Register_Map#Misc_Registers
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*
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* The QEMU model of the Milkymist UART block by Michael Walle
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* is used as a template.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "sysemu/char.h"
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#include "hw/char/digic-uart.h"
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enum {
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ST_RX_RDY = (1 << 0),
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ST_TX_RDY = (1 << 1),
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};
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static uint64_t digic_uart_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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DigicUartState *s = opaque;
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uint64_t ret = 0;
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addr >>= 2;
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switch (addr) {
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case R_RX:
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s->reg_st &= ~(ST_RX_RDY);
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ret = s->reg_rx;
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break;
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case R_ST:
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ret = s->reg_st;
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"digic-uart: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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}
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return ret;
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}
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static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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DigicUartState *s = opaque;
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unsigned char ch = value;
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addr >>= 2;
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switch (addr) {
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case R_TX:
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if (s->chr) {
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qemu_chr_fe_write_all(s->chr, &ch, 1);
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}
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break;
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case R_ST:
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/*
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* Ignore write to R_ST.
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*
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* The point is that this register is actively used
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* during receiving and transmitting symbols,
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* but we don't know the function of most of bits.
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*
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* Ignoring writes to R_ST is only a simplification
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* of the model. It has no perceptible side effects
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* for existing guests.
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*/
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"digic-uart: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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}
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}
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static const MemoryRegionOps uart_mmio_ops = {
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.read = digic_uart_read,
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.write = digic_uart_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int uart_can_rx(void *opaque)
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{
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DigicUartState *s = opaque;
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return !(s->reg_st & ST_RX_RDY);
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}
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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DigicUartState *s = opaque;
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assert(uart_can_rx(opaque));
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s->reg_st |= ST_RX_RDY;
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s->reg_rx = *buf;
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}
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static void uart_event(void *opaque, int event)
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{
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}
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static void digic_uart_reset(DeviceState *d)
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{
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DigicUartState *s = DIGIC_UART(d);
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s->reg_rx = 0;
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s->reg_st = ST_TX_RDY;
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}
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static void digic_uart_realize(DeviceState *dev, Error **errp)
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{
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DigicUartState *s = DIGIC_UART(dev);
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s->chr = qemu_char_get_next_serial();
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
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}
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}
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static void digic_uart_init(Object *obj)
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{
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DigicUartState *s = DIGIC_UART(obj);
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memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
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TYPE_DIGIC_UART, 0x18);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->regs_region);
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}
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static const VMStateDescription vmstate_digic_uart = {
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.name = "digic-uart",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(reg_rx, DigicUartState),
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VMSTATE_UINT32(reg_st, DigicUartState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void digic_uart_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = digic_uart_realize;
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dc->reset = digic_uart_reset;
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dc->vmsd = &vmstate_digic_uart;
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}
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static const TypeInfo digic_uart_info = {
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.name = TYPE_DIGIC_UART,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(DigicUartState),
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.instance_init = digic_uart_init,
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.class_init = digic_uart_class_init,
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};
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static void digic_uart_register_types(void)
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{
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type_register_static(&digic_uart_info);
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}
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type_init(digic_uart_register_types)
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@ -21,6 +21,7 @@
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#include "cpu.h"
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#include "cpu.h"
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#include "hw/timer/digic-timer.h"
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#include "hw/timer/digic-timer.h"
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#include "hw/char/digic-uart.h"
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#define TYPE_DIGIC "digic"
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#define TYPE_DIGIC "digic"
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@ -36,6 +37,7 @@ typedef struct DigicState {
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ARMCPU cpu;
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ARMCPU cpu;
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DigicTimerState timer[DIGIC4_NB_TIMERS];
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DigicTimerState timer[DIGIC4_NB_TIMERS];
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DigicUartState uart;
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} DigicState;
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} DigicState;
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#endif /* HW_ARM_DIGIC_H */
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#endif /* HW_ARM_DIGIC_H */
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@ -0,0 +1,47 @@
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/*
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* Canon DIGIC UART block declarations.
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*
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* Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef HW_CHAR_DIGIC_UART_H
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#define HW_CHAR_DIGIC_UART_H
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#include "hw/sysbus.h"
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#include "qemu/typedefs.h"
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#define TYPE_DIGIC_UART "digic-uart"
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#define DIGIC_UART(obj) \
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OBJECT_CHECK(DigicUartState, (obj), TYPE_DIGIC_UART)
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enum {
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R_TX = 0x00,
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R_RX,
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R_ST = (0x14 >> 2),
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R_MAX
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};
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typedef struct DigicUartState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion regs_region;
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CharDriverState *chr;
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uint32_t reg_rx;
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uint32_t reg_st;
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} DigicUartState;
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#endif /* HW_CHAR_DIGIC_UART_H */
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