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hw/i*: pass owner to memory_region_init* functions 

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2013-06-06 21:25:08 -04:00
parent b716368778
commit 1437c94b26
41 changed files with 111 additions and 87 deletions
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2
hw/i2c/bitbang_i2c.c
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@ -209,7 +209,7 @@ static int gpio_i2c_init(SysBusDevice *dev)
GPIOI2CState *s = FROM_SYSBUS(GPIOI2CState, dev);
i2c_bus *bus;
memory_region_init(&s->dummy_iomem, NULL, "gpio_i2c", 0);
memory_region_init(&s->dummy_iomem, OBJECT(s), "gpio_i2c", 0);
sysbus_init_mmio(dev, &s->dummy_iomem);
bus = i2c_init_bus(&dev->qdev, "i2c");

4
hw/i2c/exynos4210_i2c.c
View File

@ -301,8 +301,8 @@ static int exynos4210_i2c_realize(SysBusDevice *dev)
{
Exynos4210I2CState *s = EXYNOS4_I2C(dev);
memory_region_init_io(&s->iomem, NULL, &exynos4210_i2c_ops, s, TYPE_EXYNOS4_I2C,
EXYNOS4_I2C_MEM_SIZE);
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_i2c_ops, s,
TYPE_EXYNOS4_I2C, EXYNOS4_I2C_MEM_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->bus = i2c_init_bus(&dev->qdev, "i2c");

2
hw/i2c/omap_i2c.c
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@ -448,7 +448,7 @@ static int omap_i2c_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->drq[0]);
sysbus_init_irq(dev, &s->drq[1]);
memory_region_init_io(&s->iomem, NULL, &omap_i2c_ops, s, "omap.i2c",
memory_region_init_io(&s->iomem, OBJECT(s), &omap_i2c_ops, s, "omap.i2c",
(s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
sysbus_init_mmio(dev, &s->iomem);
s->bus = i2c_init_bus(&dev->qdev, NULL);

3
hw/i2c/pm_smbus.c
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@ -181,5 +181,6 @@ static const MemoryRegionOps pm_smbus_ops = {
void pm_smbus_init(DeviceState *parent, PMSMBus *smb)
{
smb->smbus = i2c_init_bus(parent, "i2c");
memory_region_init_io(&smb->io, NULL, &pm_smbus_ops, smb, "pm-smbus", 64);
memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb,
"pm-smbus", 64);
}

2
hw/i2c/versatile_i2c.c
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@ -79,7 +79,7 @@ static int versatile_i2c_init(SysBusDevice *dev)
bus = i2c_init_bus(&dev->qdev, "i2c");
s->bitbang = bitbang_i2c_init(bus);
memory_region_init_io(&s->iomem, NULL, &versatile_i2c_ops, s,
memory_region_init_io(&s->iomem, OBJECT(s), &versatile_i2c_ops, s,
"versatile_i2c", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
return 0;

28
hw/i386/kvm/pci-assign.c
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@ -298,8 +298,8 @@ static void assigned_dev_iomem_setup(PCIDevice *pci_dev, int region_num,
PCIRegion *real_region = &r_dev->real_device.regions[region_num];
if (e_size > 0) {
memory_region_init(&region->container, NULL, "assigned-dev-container",
e_size);
memory_region_init(&region->container, OBJECT(pci_dev),
"assigned-dev-container", e_size);
memory_region_add_subregion(&region->container, 0, &region->real_iomem);
/* deal with MSI-X MMIO page */
@ -329,9 +329,10 @@ static void assigned_dev_ioport_setup(PCIDevice *pci_dev, int region_num,
AssignedDevRegion *region = &r_dev->v_addrs[region_num];
region->e_size = size;
memory_region_init(&region->container, NULL, "assigned-dev-container", size);
memory_region_init_io(&region->real_iomem, NULL, &assigned_dev_ioport_ops,
r_dev->v_addrs + region_num,
memory_region_init(&region->container, OBJECT(pci_dev),
"assigned-dev-container", size);
memory_region_init_io(&region->real_iomem, OBJECT(pci_dev),
&assigned_dev_ioport_ops, r_dev->v_addrs + region_num,
"assigned-dev-iomem", size);
memory_region_add_subregion(&region->container, 0, &region->real_iomem);
}
@ -478,8 +479,9 @@ static int assigned_dev_register_regions(PCIRegion *io_regions,
"4K. You might experience some performance hit "
"due to that.",
i, cur_region->base_addr, cur_region->size);
memory_region_init_io(&pci_dev->v_addrs[i].real_iomem, NULL,
&slow_bar_ops, &pci_dev->v_addrs[i],
memory_region_init_io(&pci_dev->v_addrs[i].real_iomem,
OBJECT(pci_dev), &slow_bar_ops,
&pci_dev->v_addrs[i],
"assigned-dev-slow-bar",
cur_region->size);
} else {
@ -487,9 +489,9 @@ static int assigned_dev_register_regions(PCIRegion *io_regions,
char name[32];
snprintf(name, sizeof(name), "%s.bar%d",
object_get_typename(OBJECT(pci_dev)), i);
memory_region_init_ram_ptr(&pci_dev->v_addrs[i].real_iomem, NULL,
name, cur_region->size,
virtbase);
memory_region_init_ram_ptr(&pci_dev->v_addrs[i].real_iomem,
OBJECT(pci_dev), name,
cur_region->size, virtbase);
vmstate_register_ram(&pci_dev->v_addrs[i].real_iomem,
&pci_dev->dev.qdev);
}
@ -1650,8 +1652,8 @@ static int assigned_dev_register_msix_mmio(AssignedDevice *dev)
assigned_dev_msix_reset(dev);
memory_region_init_io(&dev->mmio, NULL, &assigned_dev_msix_mmio_ops, dev,
"assigned-dev-msix", MSIX_PAGE_SIZE);
memory_region_init_io(&dev->mmio, OBJECT(dev), &assigned_dev_msix_mmio_ops,
dev, "assigned-dev-msix", MSIX_PAGE_SIZE);
return 0;
}
@ -1916,7 +1918,7 @@ static void assigned_dev_load_option_rom(AssignedDevice *dev)
snprintf(name, sizeof(name), "%s.rom",
object_get_typename(OBJECT(dev)));
memory_region_init_ram(&dev->dev.rom, NULL, name, st.st_size);
memory_region_init_ram(&dev->dev.rom, OBJECT(dev), name, st.st_size);
vmstate_register_ram(&dev->dev.rom, &dev->dev.qdev);
ptr = memory_region_get_ram_ptr(&dev->dev.rom);
memset(ptr, 0xff, st.st_size);

6
hw/i386/kvmvapic.c
View File

@ -601,8 +601,8 @@ static void vapic_map_rom_writable(VAPICROMState *s)
rom_paddr &= TARGET_PAGE_MASK;
rom_size = TARGET_PAGE_ALIGN(rom_size);
memory_region_init_alias(&s->rom, NULL, "kvmvapic-rom", section.mr, rom_paddr,
rom_size);
memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr,
rom_paddr, rom_size);
memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000);
s->rom_mapped_writable = true;
memory_region_unref(section.mr);
@ -703,7 +703,7 @@ static int vapic_init(SysBusDevice *dev)
{
VAPICROMState *s = VAPIC(dev);
memory_region_init_io(&s->io, NULL, &vapic_ops, s, "kvmvapic", 2);
memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2);
sysbus_add_io(dev, VAPIC_IO_PORT, &s->io);
sysbus_init_ioports(dev, VAPIC_IO_PORT, 2);

2
hw/i386/pc.c
View File

@ -525,7 +525,7 @@ static void port92_initfn(Object *obj)
{
Port92State *s = PORT92(obj);
memory_region_init_io(&s->io, NULL, &port92_ops, s, "port92", 1);
memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
s->outport = 0;
}

6
hw/ide/ahci.c
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@ -1158,8 +1158,10 @@ void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
s->dev = g_malloc0(sizeof(AHCIDevice) * ports);
ahci_reg_init(s);
/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
memory_region_init_io(&s->mem, NULL, &ahci_mem_ops, s, "ahci", AHCI_MEM_BAR_SIZE);
memory_region_init_io(&s->idp, NULL, &ahci_idp_ops, s, "ahci-idp", 32);
memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
"ahci", AHCI_MEM_BAR_SIZE);
memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
"ahci-idp", 32);
irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);

13
hw/ide/cmd646.c
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@ -117,8 +117,10 @@ static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
bar->bus = bus;
bar->pci_dev = d;
memory_region_init_io(&bar->cmd, NULL, &cmd646_cmd_ops, bar, "cmd646-cmd", 4);
memory_region_init_io(&bar->data, NULL, &cmd646_data_ops, bar, "cmd646-data", 8);
memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
"cmd646-cmd", 4);
memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
"cmd646-data", 8);
}
static uint64_t bmdma_read(void *opaque, hwaddr addr,
@ -203,13 +205,14 @@ static void bmdma_setup_bar(PCIIDEState *d)
BMDMAState *bm;
int i;
memory_region_init(&d->bmdma_bar, NULL, "cmd646-bmdma", 16);
memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
for(i = 0;i < 2; i++) {
bm = &d->bmdma[i];
memory_region_init_io(&bm->extra_io, NULL, &cmd646_bmdma_ops, bm,
memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
"cmd646-bmdma-bus", 4);
memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
memory_region_init_io(&bm->addr_ioport, NULL, &bmdma_addr_ioport_ops, bm,
memory_region_init_io(&bm->addr_ioport, OBJECT(d),
&bmdma_addr_ioport_ops, bm,
"cmd646-bmdma-ioport", 4);
memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
}

2
hw/ide/macio.c
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@ -335,7 +335,7 @@ static void macio_ide_initfn(Object *obj)
MACIOIDEState *s = MACIO_IDE(obj);
ide_bus_new(&s->bus, DEVICE(obj), 0, 2);
memory_region_init_io(&s->mem, NULL, &pmac_ide_ops, s, "pmac-ide", 0x1000);
memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
sysbus_init_mmio(d, &s->mem);
sysbus_init_irq(d, &s->irq);
sysbus_init_irq(d, &s->dma_irq);

4
hw/ide/mmio.c
View File

@ -124,9 +124,9 @@ static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
ide_init2(&s->bus, s->irq);
memory_region_init_io(&s->iomem1, NULL, &mmio_ide_ops, s,
memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s,
"ide-mmio.1", 16 << s->shift);
memory_region_init_io(&s->iomem2, NULL, &mmio_ide_cs_ops, s,
memory_region_init_io(&s->iomem2, OBJECT(s), &mmio_ide_cs_ops, s,
"ide-mmio.2", 2 << s->shift);
sysbus_init_mmio(d, &s->iomem1);
sysbus_init_mmio(d, &s->iomem2);

8
hw/ide/piix.c
View File

@ -90,15 +90,15 @@ static void bmdma_setup_bar(PCIIDEState *d)
{
int i;
memory_region_init(&d->bmdma_bar, NULL, "piix-bmdma-container", 16);
memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
for(i = 0;i < 2; i++) {
BMDMAState *bm = &d->bmdma[i];
memory_region_init_io(&bm->extra_io, NULL, &piix_bmdma_ops, bm,
memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
"piix-bmdma", 4);
memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
memory_region_init_io(&bm->addr_ioport, NULL, &bmdma_addr_ioport_ops, bm,
"bmdma", 4);
memory_region_init_io(&bm->addr_ioport, OBJECT(d),
&bmdma_addr_ioport_ops, bm, "bmdma", 4);
memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
}
}

8
hw/ide/via.c
View File

@ -92,15 +92,15 @@ static void bmdma_setup_bar(PCIIDEState *d)
{
int i;
memory_region_init(&d->bmdma_bar, NULL, "via-bmdma-container", 16);
memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
for(i = 0;i < 2; i++) {
BMDMAState *bm = &d->bmdma[i];
memory_region_init_io(&bm->extra_io, NULL, &via_bmdma_ops, bm,
memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
"via-bmdma", 4);
memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
memory_region_init_io(&bm->addr_ioport, NULL, &bmdma_addr_ioport_ops, bm,
"bmdma", 4);
memory_region_init_io(&bm->addr_ioport, OBJECT(d),
&bmdma_addr_ioport_ops, bm, "bmdma", 4);
memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
}
}

6
hw/input/milkymist-softusb.c
View File

@ -265,17 +265,17 @@ static int milkymist_softusb_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->regs_region, NULL, &softusb_mmio_ops, s,
memory_region_init_io(&s->regs_region, OBJECT(s), &softusb_mmio_ops, s,
"milkymist-softusb", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
/* register pmem and dmem */
memory_region_init_ram(&s->pmem, NULL, "milkymist-softusb.pmem",
memory_region_init_ram(&s->pmem, OBJECT(s), "milkymist-softusb.pmem",
s->pmem_size);
vmstate_register_ram_global(&s->pmem);
s->pmem_ptr = memory_region_get_ram_ptr(&s->pmem);
sysbus_init_mmio(dev, &s->pmem);
memory_region_init_ram(&s->dmem, NULL, "milkymist-softusb.dmem",
memory_region_init_ram(&s->dmem, OBJECT(s), "milkymist-softusb.dmem",
s->dmem_size);
vmstate_register_ram_global(&s->dmem);
s->dmem_ptr = memory_region_get_ram_ptr(&s->dmem);

6
hw/input/pckbd.c
View File

@ -494,8 +494,10 @@ static void i8042_initfn(Object *obj)
ISAKBDState *isa_s = I8042(obj);
KBDState *s = &isa_s->kbd;
memory_region_init_io(isa_s->io + 0, NULL, &i8042_data_ops, s, "i8042-data", 1);
memory_region_init_io(isa_s->io + 1, NULL, &i8042_cmd_ops, s, "i8042-cmd", 1);
memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
"i8042-data", 1);
memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
"i8042-cmd", 1);
}
static void i8042_realizefn(DeviceState *dev, Error **errp)

2
hw/input/pl050.c
View File

@ -137,7 +137,7 @@ static int pl050_init(SysBusDevice *dev, int is_mouse)
{
pl050_state *s = FROM_SYSBUS(pl050_state, dev);
memory_region_init_io(&s->iomem, NULL, &pl050_ops, s, "pl050", 0x1000);
memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->is_mouse = is_mouse;

2
hw/intc/apic.c
View File

@ -873,7 +873,7 @@ static const MemoryRegionOps apic_io_ops = {
static void apic_init(APICCommonState *s)
{
memory_region_init_io(&s->io_memory, NULL, &apic_io_ops, s, "apic-msi",
memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
APIC_SPACE_SIZE);
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);

9
hw/intc/arm_gic.c
View File

@ -656,7 +656,8 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq)
for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
memory_region_init_io(&s->iomem, NULL, &gic_dist_ops, s, "gic_dist", 0x1000);
memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s,
"gic_dist", 0x1000);
}
static void arm_gic_realize(DeviceState *dev, Error **errp)
@ -682,12 +683,12 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
* GIC v2 defines a larger memory region (0x1000) so this will need
* to be extended when we implement A15.
*/
memory_region_init_io(&s->cpuiomem[0], NULL, &gic_thiscpu_ops, s,
memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s,
"gic_cpu", 0x100);
for (i = 0; i < NUM_CPU(s); i++) {
s->backref[i] = s;
memory_region_init_io(&s->cpuiomem[i+1], NULL, &gic_cpu_ops, &s->backref[i],
"gic_cpu", 0x100);
memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops,
&s->backref[i], "gic_cpu", 0x100);
}
/* Distributor */
sysbus_init_mmio(sbd, &s->iomem);

6
hw/intc/arm_gic_kvm.c
View File

@ -120,7 +120,8 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
sysbus_init_irq(sbd, &s->parent_irq[i]);
}
/* Distributor */
memory_region_init_reservation(&s->iomem, NULL, "kvm-gic_dist", 0x1000);
memory_region_init_reservation(&s->iomem, OBJECT(s),
"kvm-gic_dist", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
kvm_arm_register_device(&s->iomem,
(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
@ -129,7 +130,8 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
* provide the "interface for core #N" memory regions, because
* cores with a VGIC don't have those.
*/
memory_region_init_reservation(&s->cpuiomem[0], NULL, "kvm-gic_cpu", 0x1000);
memory_region_init_reservation(&s->cpuiomem[0], OBJECT(s),
"kvm-gic_cpu", 0x1000);
sysbus_init_mmio(sbd, &s->cpuiomem[0]);
kvm_arm_register_device(&s->cpuiomem[0],
(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)

7
hw/intc/armv7m_nvic.c
View File

@ -487,17 +487,18 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
* We use overlaying to put the GIC like registers
* over the top of the system control register region.
*/
memory_region_init(&s->container, NULL, "nvic", 0x1000);
memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000);
/* The system register region goes at the bottom of the priority
* stack as it covers the whole page.
*/
memory_region_init_io(&s->sysregmem, NULL, &nvic_sysreg_ops, s,
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
"nvic_sysregs", 0x1000);
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
/* Alias the GIC region so we can get only the section of it
* we need, and layer it on top of the system register region.
*/
memory_region_init_alias(&s->gic_iomem_alias, NULL, "nvic-gic", &s->gic.iomem,
memory_region_init_alias(&s->gic_iomem_alias, OBJECT(s),
"nvic-gic", &s->gic.iomem,
0x100, 0xc00);
memory_region_add_subregion_overlap(&s->container, 0x100,
&s->gic_iomem_alias, 1);

3
hw/intc/etraxfs_pic.c
View File

@ -146,7 +146,8 @@ static int etraxfs_pic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_nmi);
memory_region_init_io(&s->mmio, NULL, &pic_ops, s, "etraxfs-pic", R_MAX * 4);
memory_region_init_io(&s->mmio, OBJECT(s), &pic_ops, s,
"etraxfs-pic", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
return 0;
}

2
hw/intc/exynos4210_combiner.c
View File

@ -417,7 +417,7 @@ static int exynos4210_combiner_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->output_irq[i]);
}
memory_region_init_io(&s->iomem, NULL, &exynos4210_combiner_ops, s,
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_combiner_ops, s,
"exynos4210-combiner", IIC_REGION_SIZE);
sysbus_init_mmio(dev, &s->iomem);

8
hw/intc/exynos4210_gic.c
View File

@ -299,15 +299,15 @@ static int exynos4210_gic_init(SysBusDevice *dev)
qdev_init_gpio_in(&s->busdev.qdev, exynos4210_gic_set_irq,
EXYNOS4210_GIC_NIRQ - 32);
memory_region_init(&s->cpu_container, NULL, "exynos4210-cpu-container",
memory_region_init(&s->cpu_container, OBJECT(s), "exynos4210-cpu-container",
EXYNOS4210_EXT_GIC_CPU_REGION_SIZE);
memory_region_init(&s->dist_container, NULL, "exynos4210-dist-container",
memory_region_init(&s->dist_container, OBJECT(s), "exynos4210-dist-container",
EXYNOS4210_EXT_GIC_DIST_REGION_SIZE);
for (i = 0; i < s->num_cpu; i++) {
/* Map CPU interface per SMP Core */
sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
memory_region_init_alias(&s->cpu_alias[i], NULL,
memory_region_init_alias(&s->cpu_alias[i], OBJECT(s),
cpu_alias_name,
sysbus_mmio_get_region(busdev, 1),
0,
@ -317,7 +317,7 @@ static int exynos4210_gic_init(SysBusDevice *dev)
/* Map Distributor per SMP Core */
sprintf(dist_alias_name, "%s%x", dist_prefix, i);
memory_region_init_alias(&s->dist_alias[i], NULL,
memory_region_init_alias(&s->dist_alias[i], OBJECT(s),
dist_alias_name,
sysbus_mmio_get_region(busdev, 0),
0,

2
hw/intc/grlib_irqmp.c
View File

@ -344,7 +344,7 @@ static int grlib_irqmp_init(SysBusDevice *dev)
return -1;
}
memory_region_init_io(&irqmp->iomem, NULL, &grlib_irqmp_ops, irqmp,
memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
"irqmp", IRQMP_REG_SIZE);
irqmp->state = g_malloc0(sizeof *irqmp->state);

6
hw/intc/i8259.c
View File

@ -417,8 +417,10 @@ static void pic_realize(DeviceState *dev, Error **err)
PICCommonState *s = PIC_COMMON(dev);
PICClass *pc = PIC_GET_CLASS(dev);
memory_region_init_io(&s->base_io, NULL, &pic_base_ioport_ops, s, "pic", 2);
memory_region_init_io(&s->elcr_io, NULL, &pic_elcr_ioport_ops, s, "elcr", 1);
memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s,
"pic", 2);
memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s,
"elcr", 1);
qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out));
qdev_init_gpio_in(dev, pic_set_irq, 8);

3
hw/intc/imx_avic.c
View File

@ -372,7 +372,8 @@ static int imx_avic_init(SysBusDevice *dev)
{
IMXAVICState *s = FROM_SYSBUS(IMXAVICState, dev);
memory_region_init_io(&s->iomem, NULL, &imx_avic_ops, s, "imx_avic", 0x1000);
memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s,
"imx_avic", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);

3
hw/intc/ioapic.c
View File

@ -227,7 +227,8 @@ static const MemoryRegionOps ioapic_io_ops = {
static void ioapic_init(IOAPICCommonState *s, int instance_no)
{
memory_region_init_io(&s->io_memory, NULL, &ioapic_io_ops, s, "ioapic", 0x1000);
memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
"ioapic", 0x1000);
qdev_init_gpio_in(&s->busdev.qdev, ioapic_set_irq, IOAPIC_NUM_PINS);

4
hw/intc/omap_intc.c
View File

@ -367,7 +367,7 @@ static int omap_intc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_intr[0]);
sysbus_init_irq(dev, &s->parent_intr[1]);
qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
memory_region_init_io(&s->mmio, NULL, &omap_inth_mem_ops, s,
memory_region_init_io(&s->mmio, OBJECT(s), &omap_inth_mem_ops, s,
"omap-intc", s->size);
sysbus_init_mmio(dev, &s->mmio);
return 0;
@ -609,7 +609,7 @@ static int omap2_intc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_intr[0]);
sysbus_init_irq(dev, &s->parent_intr[1]);
qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
memory_region_init_io(&s->mmio, NULL, &omap2_inth_mem_ops, s,
memory_region_init_io(&s->mmio, OBJECT(s), &omap2_inth_mem_ops, s,
"omap2-intc", 0x1000);
sysbus_init_mmio(dev, &s->mmio);
return 0;

6
hw/intc/openpic.c
View File

@ -1516,8 +1516,8 @@ static void map_list(OpenPICState *opp, const MemReg *list, int *count)
while (list->name) {
assert(*count < ARRAY_SIZE(opp->sub_io_mem));
memory_region_init_io(&opp->sub_io_mem[*count], NULL, list->ops, opp,
list->name, list->size);
memory_region_init_io(&opp->sub_io_mem[*count], OBJECT(opp), list->ops,
opp, list->name, list->size);
memory_region_add_subregion(&opp->mem, list->start_addr,
&opp->sub_io_mem[*count]);
@ -1531,7 +1531,7 @@ static void openpic_init(Object *obj)
{
OpenPICState *opp = OPENPIC(obj);
memory_region_init(&opp->mem, NULL, "openpic", 0x40000);
memory_region_init(&opp->mem, obj, "openpic", 0x40000);
}
static void openpic_realize(DeviceState *dev, Error **errp)

2
hw/intc/openpic_kvm.c
View File

@ -155,7 +155,7 @@ static void kvm_openpic_init(Object *obj)
{
KVMOpenPICState *opp = KVM_OPENPIC(obj);
memory_region_init_io(&opp->mem, NULL, &kvm_openpic_mem_ops, opp,
memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
"kvm-openpic", 0x40000);
}

2
hw/intc/pl190.c
View File

@ -236,7 +236,7 @@ static int pl190_init(SysBusDevice *dev)
{
pl190_state *s = FROM_SYSBUS(pl190_state, dev);
memory_region_init_io(&s->iomem, NULL, &pl190_ops, s, "pl190", 0x1000);
memory_region_init_io(&s->iomem, OBJECT(s), &pl190_ops, s, "pl190", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
sysbus_init_irq(dev, &s->irq);

2
hw/intc/puv3_intc.c
View File

@ -106,7 +106,7 @@ static int puv3_intc_init(SysBusDevice *dev)
s->reg_ICMR = 0;
s->reg_ICPR = 0;
memory_region_init_io(&s->iomem, NULL, &puv3_intc_ops, s, "puv3_intc",
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);

3
hw/intc/realview_gic.c
View File

@ -43,7 +43,8 @@ static int realview_gic_init(SysBusDevice *dev)
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, realview_gic_set_irq, numirq - 32);
memory_region_init(&s->container, NULL, "realview-gic-container", 0x2000);
memory_region_init(&s->container, OBJECT(s),
"realview-gic-container", 0x2000);
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(busdev, 1));
memory_region_add_subregion(&s->container, 0x1000,

5
hw/intc/slavio_intctl.c
View File

@ -426,7 +426,7 @@ static int slavio_intctl_init1(SysBusDevice *dev)
char slave_name[45];
qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
memory_region_init_io(&s->iomem, NULL, &slavio_intctlm_mem_ops, s,
memory_region_init_io(&s->iomem, OBJECT(s), &slavio_intctlm_mem_ops, s,
"master-interrupt-controller", INTCTLM_SIZE);
sysbus_init_mmio(dev, &s->iomem);
@ -436,7 +436,8 @@ static int slavio_intctl_init1(SysBusDevice *dev)
for (j = 0; j < MAX_PILS; j++) {
sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
}
memory_region_init_io(&s->slaves[i].iomem, NULL, &slavio_intctl_mem_ops,
memory_region_init_io(&s->slaves[i].iomem, OBJECT(s),
&slavio_intctl_mem_ops,
&s->slaves[i], slave_name, INTCTL_SIZE);
sysbus_init_mmio(dev, &s->slaves[i].iomem);
s->slaves[i].cpu = i;

3
hw/intc/xilinx_intc.c
View File

@ -160,7 +160,8 @@ static int xilinx_intc_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
sysbus_init_irq(dev, &p->parent_irq);
memory_region_init_io(&p->mmio, NULL, &pic_ops, p, "xlnx.xps-intc", R_MAX * 4);
memory_region_init_io(&p->mmio, OBJECT(p), &pic_ops, p, "xlnx.xps-intc",
R_MAX * 4);
sysbus_init_mmio(dev, &p->mmio);
return 0;
}

2
hw/isa/apm.c
View File

@ -96,7 +96,7 @@ void apm_init(PCIDevice *dev, APMState *apm, apm_ctrl_changed_t callback,
apm->arg = arg;
/* ioport 0xb2, 0xb3 */
memory_region_init_io(&apm->io, NULL, &apm_ops, apm, "apm-io", 2);
memory_region_init_io(&apm->io, OBJECT(dev), &apm_ops, apm, "apm-io", 2);
memory_region_add_subregion(pci_address_space_io(dev), APM_CNT_IOPORT,
&apm->io);
}

6
hw/isa/i82378.c
View File

@ -221,10 +221,12 @@ static int pci_i82378_init(PCIDevice *dev)
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
memory_region_init_io(&s->io, NULL, &i82378_io_ops, s, "i82378-io", 0x00010000);
memory_region_init_io(&s->io, OBJECT(pci), &i82378_io_ops, s,
"i82378-io", 0x00010000);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io);
memory_region_init_io(&s->mem, NULL, &i82378_mem_ops, s, "i82378-mem", 0x01000000);
memory_region_init_io(&s->mem, OBJECT(pci), &i82378_mem_ops, s,
"i82378-mem", 0x01000000);
pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
/* Make I/O address read only */

4
hw/isa/lpc_ich9.c
View File

@ -535,7 +535,7 @@ static int ich9_lpc_initfn(PCIDevice *d)
pci_set_long(d->wmask + ICH9_LPC_PMBASE,
ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
memory_region_init_io(&lpc->rbca_mem, NULL, &rbca_mmio_ops, lpc,
memory_region_init_io(&lpc->rbca_mem, OBJECT(d), &rbca_mmio_ops, lpc,
"lpc-rbca-mmio", ICH9_CC_SIZE);
lpc->isa_bus = isa_bus;
@ -546,7 +546,7 @@ static int ich9_lpc_initfn(PCIDevice *d)
lpc->machine_ready.notify = ich9_lpc_machine_ready;
qemu_add_machine_init_done_notifier(&lpc->machine_ready);
memory_region_init_io(&lpc->rst_cnt_mem, NULL, &ich9_rst_cnt_ops, lpc,
memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
"lpc-reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(d),
ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,

2
hw/isa/pc87312.c
View File

@ -352,7 +352,7 @@ static void pc87312_initfn(Object *obj)
{
PC87312State *s = PC87312(obj);
memory_region_init_io(&s->io, NULL, &pc87312_io_ops, s, "pc87312", 2);
memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2);
}
static const VMStateDescription vmstate_pc87312 = {

2
hw/isa/vt82c686.c
View File

@ -356,7 +356,7 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
apm_init(dev, &s->apm, NULL, s);
memory_region_init(&s->io, NULL, "vt82c686-pm", 64);
memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
memory_region_set_enabled(&s->io, false);
memory_region_add_subregion(get_system_io(), 0, &s->io);