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target/arm: Convert T32 ADDW/SUBW 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:09 -07:00 committed by Peter Maydell
parent 2cde9ea57d
commit 145952e87f
3 changed files with 33 additions and 11 deletions
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1
target/arm/a32.decode
View File

@ -30,6 +30,7 @@
&rrrr rd rn rm ra
&rrr rd rn rm
&rr rd rm
&ri rd imm
&r rm
&i imm
&msr_reg rn r mask

19
target/arm/t32.decode
View File

@ -27,6 +27,7 @@
&rrrr !extern rd rn rm ra
&rrr !extern rd rn rm
&rr !extern rd rm
&ri !extern rd imm
&r !extern rm
&i !extern imm
&msr_reg !extern rn r mask
@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot
}
RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
# Data processing (plain binary immediate)
%imm12_26_12_0 26:1 12:3 0:8
%neg12_26_12_0 26:1 12:3 0:8 !function=negate
@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \
&s_rri_rot imm=%imm12_26_12_0 rot=0 s=0
{
ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \
&ri imm=%imm12_26_12_0
ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12
}
{
ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \
&ri imm=%neg12_26_12_0
SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12
}
# Multiply and multiply accumulate
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0

24
target/arm/translate.c
View File

@ -7648,6 +7648,11 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
* Constant expanders for the decoders.
*/
static int negate(DisasContext *s, int x)
{
return -x;
}
static int times_2(DisasContext *s, int x)
{
return x * 2;
@ -8004,6 +8009,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a)
#undef DO_ANY2
#undef DO_CMP2
static bool trans_ADR(DisasContext *s, arg_ri *a)
{
store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm));
return true;
}
/*
* Multiply and multiply accumulate
*/
@ -10724,17 +10735,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
store_reg(s, rd, tmp);
} else {
/* Add/sub 12-bit immediate. */
if (insn & (1 << 23)) {
imm = -imm;
}
tmp = add_reg_for_lit(s, rn, imm);
if (rn == 13 && rd == 13) {
/* ADD SP, SP, imm or SUB SP, SP, imm */
store_sp_checked(s, tmp);
} else {
store_reg(s, rd, tmp);
}
/* Add/sub 12-bit immediate, in decodetree */
goto illegal_op;
}
}
} else {