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target/mips: Fix emulation of nanoMIPS BNEC[32] instruction 

If both rs and rt are the same register, the nanoMIPS instruction
BNEC[32] rs, rt, address is equivalent to NOP (branch is not taken and
there is no delay slot). This commit provides such behavior. Without
this commit, this scenario results in an incorrect behavior.

Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-5-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Dragan Mladjenovic 2022-05-04 13:04:00 +02:00 committed by Philippe Mathieu-Daudé
parent 5de4359b4f
commit 14668cfaaf
1 changed files with 6 additions and 1 deletions
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7
target/mips/tcg/nanomips_translate.c.inc
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@ -4528,7 +4528,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 14, 2)) { switch (extract32(ctx->opcode, 14, 2)) {
case NM_BNEC: case NM_BNEC:
check_nms(ctx); check_nms(ctx);
gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s); if (rs == rt) {
/* NOP */
ctx->hflags |= MIPS_HFLAG_FBNSLOT;
} else {
gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
}
break; break;
case NM_BLTC: case NM_BLTC:
if (rs != 0 && rt != 0 && rs == rt) { if (rs != 0 && rt != 0 && rs == rt) {