OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

arm: xlnx-zynqmp: Add GEM support

Browse Source 
There are 4x Cadence GEMs in ZynqMP. Add them.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Crosthwaite 2015-05-14 19:23:12 -07:00 committed by Peter Maydell
parent f49856d4e6
commit 14ca2e462e
2 changed files with 38 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
hw/arm/xlnx-zynqmp.c
View File

@ -28,6 +28,14 @@
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};
static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
57, 59, 61, 63,
};
typedef struct XlnxZynqMPGICRegion {
int region_index;
uint32_t address;
@ -57,6 +65,11 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
}
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@ -64,6 +77,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
MemoryRegion *system_memory = get_system_memory();
uint8_t i;
qemu_irq gic_spi[GIC_NUM_SPI_INTR];
Error *err = NULL;
qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
@ -127,6 +141,27 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
}
for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
NICInfo *nd = &nd_table[i];
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
}
object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
if (err) {
error_propagate((errp), (err));
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
gic_spi[gem_intr[i]]);
}
}
static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)

3
include/hw/arm/xlnx-zynqmp.h
View File

@ -20,12 +20,14 @@
#include "qemu-common.h"
#include "hw/arm/arm.h"
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
TYPE_XLNX_ZYNQMP)
#define XLNX_ZYNQMP_NUM_CPUS 4
#define XLNX_ZYNQMP_NUM_GEMS 4
#define XLNX_ZYNQMP_GIC_REGIONS 2
@ -46,6 +48,7 @@ typedef struct XlnxZynqMPState {
ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H