target/mips: Clean up handling of CP0 register 20
Clean up handling of CP0 register 20. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-22-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -7341,7 +7341,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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break;
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case CP0_REGISTER_20:
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case CP0_REGISTER_20:
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switch (sel) {
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switch (sel) {
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case 0:
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case CP0_REG20__XCONTEXT:
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#if defined(TARGET_MIPS64)
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#if defined(TARGET_MIPS64)
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check_insn(ctx, ISA_MIPS3);
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check_insn(ctx, ISA_MIPS3);
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
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@ -8076,7 +8076,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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break;
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case CP0_REGISTER_20:
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case CP0_REGISTER_20:
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switch (sel) {
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switch (sel) {
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case 0:
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case CP0_REG20__XCONTEXT:
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#if defined(TARGET_MIPS64)
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#if defined(TARGET_MIPS64)
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check_insn(ctx, ISA_MIPS3);
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check_insn(ctx, ISA_MIPS3);
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gen_helper_mtc0_xcontext(cpu_env, arg);
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gen_helper_mtc0_xcontext(cpu_env, arg);
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@ -8813,7 +8813,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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break;
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case CP0_REGISTER_20:
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case CP0_REGISTER_20:
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switch (sel) {
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switch (sel) {
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case 0:
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case CP0_REG20__XCONTEXT:
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check_insn(ctx, ISA_MIPS3);
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check_insn(ctx, ISA_MIPS3);
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
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register_name = "XContext";
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register_name = "XContext";
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@ -9530,7 +9530,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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break;
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case CP0_REGISTER_20:
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case CP0_REGISTER_20:
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switch (sel) {
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switch (sel) {
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case 0:
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case CP0_REG20__XCONTEXT:
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check_insn(ctx, ISA_MIPS3);
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check_insn(ctx, ISA_MIPS3);
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gen_helper_mtc0_xcontext(cpu_env, arg);
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gen_helper_mtc0_xcontext(cpu_env, arg);
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register_name = "XContext";
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register_name = "XContext";
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