hw/misc: Add a model of the Xilinx ZynqMP CRF
Add a model of the Xilinx ZynqMP CRF. At the moment this is mostly a stub model. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias
Peter Maydell
parent
4a7319b750
commit
152f0bf0c9
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@ -84,6 +84,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
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))
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softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
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softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
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specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
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'xlnx-versal-xramc.c',
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'xlnx-versal-pmc-iou-slcr.c',
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@ -0,0 +1,266 @@
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/*
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* QEMU model of the CRF - Clock Reset FPD.
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*
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* Copyright (c) 2022 Xilinx Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/misc/xlnx-zynqmp-crf.h"
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#include "target/arm/arm-powerctl.h"
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#ifndef XLNX_ZYNQMP_CRF_ERR_DEBUG
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#define XLNX_ZYNQMP_CRF_ERR_DEBUG 0
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#endif
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#define CRF_MAX_CPU 4
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static void ir_update_irq(XlnxZynqMPCRF *s)
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{
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bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
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qemu_set_irq(s->irq_ir, pending);
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}
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static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
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ir_update_irq(s);
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}
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static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IR_MASK] &= ~val;
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ir_update_irq(s);
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return 0;
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}
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static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IR_MASK] |= val;
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ir_update_irq(s);
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return 0;
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}
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static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
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uint32_t val = val64;
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uint32_t val_old = s->regs[R_RST_FPD_APU];
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unsigned int i;
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for (i = 0; i < CRF_MAX_CPU; i++) {
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uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i));
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if ((val ^ val_old) & mask) {
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if (val & mask) {
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arm_set_cpu_off(i);
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} else {
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arm_set_cpu_on_and_reset(i);
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}
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}
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}
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return val64;
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}
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static const RegisterAccessInfo crf_regs_info[] = {
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{ .name = "ERR_CTRL", .addr = A_ERR_CTRL,
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},{ .name = "IR_STATUS", .addr = A_IR_STATUS,
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.w1c = 0x1,
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.post_write = ir_status_postw,
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},{ .name = "IR_MASK", .addr = A_IR_MASK,
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.reset = 0x1,
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.ro = 0x1,
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},{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
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.pre_write = ir_enable_prew,
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},{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
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.pre_write = ir_disable_prew,
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},{ .name = "CRF_WPROT", .addr = A_CRF_WPROT,
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},{ .name = "APLL_CTRL", .addr = A_APLL_CTRL,
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.reset = 0x12c09,
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.rsvd = 0xf88c80f6,
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},{ .name = "APLL_CFG", .addr = A_APLL_CFG,
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.rsvd = 0x1801210,
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},{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG,
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.rsvd = 0x7e330000,
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},{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL,
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.reset = 0x2c09,
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.rsvd = 0xf88c80f6,
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},{ .name = "DPLL_CFG", .addr = A_DPLL_CFG,
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.rsvd = 0x1801210,
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},{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG,
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.rsvd = 0x7e330000,
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},{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL,
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.reset = 0x12809,
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.rsvd = 0xf88c80f6,
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},{ .name = "VPLL_CFG", .addr = A_VPLL_CFG,
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.rsvd = 0x1801210,
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},{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG,
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.rsvd = 0x7e330000,
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},{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
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.reset = 0x3f,
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.rsvd = 0xc0,
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.ro = 0x3f,
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},{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL,
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.reset = 0x400,
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.rsvd = 0xc0ff,
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},{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL,
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.reset = 0x400,
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.rsvd = 0xc0ff,
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},{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL,
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.reset = 0x400,
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.rsvd = 0xc0ff,
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},{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL,
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.reset = 0x3000400,
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.rsvd = 0xfcffc0f8,
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},{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL,
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.reset = 0x2500,
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.rsvd = 0xfeffc0f8,
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},{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL,
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.reset = 0x1002500,
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.rsvd = 0xfeffc0f8,
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},{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL,
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.reset = 0x1002300,
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.rsvd = 0xfec0c0f8,
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},{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL,
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.reset = 0x1032300,
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.rsvd = 0xfec0c0f8,
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},{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL,
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.reset = 0x1203200,
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.rsvd = 0xfec0c0f8,
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},{ .name = "DDR_CTRL", .addr = A_DDR_CTRL,
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.reset = 0x1000500,
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.rsvd = 0xfeffc0f8,
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},{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL,
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.reset = 0x1500,
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.rsvd = 0xf8ffc0f8,
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},{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL,
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.reset = 0x1001600,
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.rsvd = 0xfeffc0f8,
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},{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL,
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.reset = 0x1500,
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.rsvd = 0xfeffc0f8,
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},{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL,
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.reset = 0x1000500,
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.rsvd = 0xfeffc0f8,
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},{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL,
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.reset = 0x1000500,
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.rsvd = 0xfeffc0f8,
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},{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL,
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.reset = 0x1000400,
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.rsvd = 0xfeffc0f8,
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},{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL,
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.reset = 0x1000800,
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.rsvd = 0xfeffc0f8,
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},{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
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.reset = 0xa00,
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.rsvd = 0xffffc0f8,
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},
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{ .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP,
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.reset = 0xf9ffe,
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.rsvd = 0xf06001,
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},{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU,
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.reset = 0x3d0f,
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.rsvd = 0xc2f0,
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.pre_write = rst_fpd_apu_prew,
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},{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS,
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.reset = 0xf,
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.rsvd = 0xf3,
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}
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};
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static void crf_reset_enter(Object *obj, ResetType type)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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register_reset(&s->regs_info[i]);
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}
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}
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static void crf_reset_hold(Object *obj)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
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ir_update_irq(s);
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}
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static const MemoryRegionOps crf_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void crf_init(Object *obj)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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s->reg_array =
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register_init_block32(DEVICE(obj), crf_regs_info,
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ARRAY_SIZE(crf_regs_info),
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s->regs_info, s->regs,
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&crf_ops,
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XLNX_ZYNQMP_CRF_ERR_DEBUG,
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CRF_R_MAX * 4);
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sysbus_init_mmio(sbd, &s->reg_array->mem);
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sysbus_init_irq(sbd, &s->irq_ir);
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}
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static void crf_finalize(Object *obj)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
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register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_crf = {
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.name = TYPE_XLNX_ZYNQMP_CRF,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void crf_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_crf;
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rc->phases.enter = crf_reset_enter;
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rc->phases.hold = crf_reset_hold;
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}
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static const TypeInfo crf_info = {
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.name = TYPE_XLNX_ZYNQMP_CRF,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxZynqMPCRF),
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.class_init = crf_class_init,
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.instance_init = crf_init,
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.instance_finalize = crf_finalize,
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};
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static void crf_register_types(void)
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{
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type_register_static(&crf_info);
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}
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type_init(crf_register_types)
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@ -0,0 +1,211 @@
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/*
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* QEMU model of the CRF - Clock Reset FPD.
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*
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* Copyright (c) 2022 Xilinx Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*/
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#ifndef HW_MISC_XLNX_ZYNQMP_CRF_H
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#define HW_MISC_XLNX_ZYNQMP_CRF_H
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF)
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REG32(ERR_CTRL, 0x0)
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FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
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REG32(IR_STATUS, 0x4)
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FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
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REG32(IR_MASK, 0x8)
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FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
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REG32(IR_ENABLE, 0xc)
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FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
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REG32(IR_DISABLE, 0x10)
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FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
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REG32(CRF_WPROT, 0x1c)
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FIELD(CRF_WPROT, ACTIVE, 0, 1)
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REG32(APLL_CTRL, 0x20)
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FIELD(APLL_CTRL, POST_SRC, 24, 3)
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FIELD(APLL_CTRL, PRE_SRC, 20, 3)
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FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
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FIELD(APLL_CTRL, DIV2, 16, 1)
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FIELD(APLL_CTRL, FBDIV, 8, 7)
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FIELD(APLL_CTRL, BYPASS, 3, 1)
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FIELD(APLL_CTRL, RESET, 0, 1)
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REG32(APLL_CFG, 0x24)
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FIELD(APLL_CFG, LOCK_DLY, 25, 7)
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FIELD(APLL_CFG, LOCK_CNT, 13, 10)
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FIELD(APLL_CFG, LFHF, 10, 2)
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FIELD(APLL_CFG, CP, 5, 4)
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FIELD(APLL_CFG, RES, 0, 4)
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REG32(APLL_FRAC_CFG, 0x28)
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FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
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FIELD(APLL_FRAC_CFG, SEED, 22, 3)
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FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
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FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
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FIELD(APLL_FRAC_CFG, DATA, 0, 16)
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REG32(DPLL_CTRL, 0x2c)
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FIELD(DPLL_CTRL, POST_SRC, 24, 3)
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FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
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FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
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FIELD(DPLL_CTRL, DIV2, 16, 1)
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FIELD(DPLL_CTRL, FBDIV, 8, 7)
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FIELD(DPLL_CTRL, BYPASS, 3, 1)
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FIELD(DPLL_CTRL, RESET, 0, 1)
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REG32(DPLL_CFG, 0x30)
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FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
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FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
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FIELD(DPLL_CFG, LFHF, 10, 2)
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FIELD(DPLL_CFG, CP, 5, 4)
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FIELD(DPLL_CFG, RES, 0, 4)
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REG32(DPLL_FRAC_CFG, 0x34)
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FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
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FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
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FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
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FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
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FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
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REG32(VPLL_CTRL, 0x38)
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FIELD(VPLL_CTRL, POST_SRC, 24, 3)
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FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
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FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
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FIELD(VPLL_CTRL, DIV2, 16, 1)
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FIELD(VPLL_CTRL, FBDIV, 8, 7)
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FIELD(VPLL_CTRL, BYPASS, 3, 1)
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FIELD(VPLL_CTRL, RESET, 0, 1)
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REG32(VPLL_CFG, 0x3c)
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FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
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FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
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FIELD(VPLL_CFG, LFHF, 10, 2)
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FIELD(VPLL_CFG, CP, 5, 4)
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FIELD(VPLL_CFG, RES, 0, 4)
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REG32(VPLL_FRAC_CFG, 0x40)
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FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
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FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
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FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
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FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
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FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
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REG32(PLL_STATUS, 0x44)
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FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
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FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
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FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
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FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
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FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
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FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
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REG32(APLL_TO_LPD_CTRL, 0x48)
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FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
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REG32(DPLL_TO_LPD_CTRL, 0x4c)
|
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FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
|
||||
REG32(VPLL_TO_LPD_CTRL, 0x50)
|
||||
FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
|
||||
REG32(ACPU_CTRL, 0x60)
|
||||
FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
|
||||
FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
|
||||
FIELD(ACPU_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(ACPU_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DBG_TRACE_CTRL, 0x64)
|
||||
FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
|
||||
FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DBG_FPD_CTRL, 0x68)
|
||||
FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
|
||||
FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DP_VIDEO_REF_CTRL, 0x70)
|
||||
FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
|
||||
FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6)
|
||||
FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DP_AUDIO_REF_CTRL, 0x74)
|
||||
FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
|
||||
FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6)
|
||||
FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DP_STC_REF_CTRL, 0x7c)
|
||||
FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
|
||||
FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
|
||||
FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DDR_CTRL, 0x80)
|
||||
FIELD(DDR_CTRL, CLKACT, 24, 1)
|
||||
FIELD(DDR_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(DDR_CTRL, SRCSEL, 0, 3)
|
||||
REG32(GPU_REF_CTRL, 0x84)
|
||||
FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
|
||||
FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
|
||||
FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
|
||||
FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(SATA_REF_CTRL, 0xa0)
|
||||
FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
|
||||
FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(PCIE_REF_CTRL, 0xb4)
|
||||
FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
|
||||
FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(GDMA_REF_CTRL, 0xb8)
|
||||
FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
|
||||
FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DPDMA_REF_CTRL, 0xbc)
|
||||
FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
|
||||
FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(TOPSW_MAIN_CTRL, 0xc0)
|
||||
FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
|
||||
FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
|
||||
REG32(TOPSW_LSBUS_CTRL, 0xc4)
|
||||
FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
|
||||
FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DBG_TSTMP_CTRL, 0xf8)
|
||||
FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6)
|
||||
FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
|
||||
REG32(RST_FPD_TOP, 0x100)
|
||||
FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
|
||||
FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
|
||||
FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
|
||||
FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
|
||||
FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
|
||||
FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
|
||||
FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
|
||||
FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
|
||||
FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
|
||||
FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
|
||||
FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
|
||||
FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
|
||||
FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
|
||||
FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
|
||||
FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
|
||||
FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
|
||||
FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
|
||||
REG32(RST_FPD_APU, 0x104)
|
||||
FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
|
||||
FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
|
||||
FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
|
||||
FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
|
||||
FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
|
||||
FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
|
||||
FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
|
||||
FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
|
||||
FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
|
||||
REG32(RST_DDR_SS, 0x108)
|
||||
FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
|
||||
FIELD(RST_DDR_SS, APM_RESET, 2, 1)
|
||||
|
||||
#define CRF_R_MAX (R_RST_DDR_SS + 1)
|
||||
|
||||
struct XlnxZynqMPCRF {
|
||||
SysBusDevice parent_obj;
|
||||
MemoryRegion iomem;
|
||||
qemu_irq irq_ir;
|
||||
|
||||
RegisterInfoArray *reg_array;
|
||||
uint32_t regs[CRF_R_MAX];
|
||||
RegisterInfo regs_info[CRF_R_MAX];
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue