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MIPS patches queue 

- Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
 - Implement Loongson CSR instructions (Jiaxun)
 - Implement Ingenic MXU ASE v1 rev2 (Siarhei)
 - Enable GINVx support for I6400 and I6500 cores (Marcin)
 - Generalize PCI IDE controller models (Bernhard)
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Merge tag 'mips-20230710' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
- Implement Loongson CSR instructions (Jiaxun)
- Implement Ingenic MXU ASE v1 rev2 (Siarhei)
- Enable GINVx support for I6400 and I6500 cores (Marcin)
- Generalize PCI IDE controller models (Bernhard)

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* tag 'mips-20230710' of https://github.com/philmd/qemu: (44 commits)
  hw/ide/piix: Move registration of VMStateDescription to DeviceClass
  hw/ide/pci: Replace some magic numbers by constants
  hw/ide: Extract bmdma_status_writeb()
  hw/ide: Extract IDEBus assignment into bmdma_init()
  hw/isa/vt82c686: Remove via_isa_set_irq()
  hw/ide/via: Wire up IDE legacy interrupts in host device
  hw/ide/pci: Expose legacy interrupts as named GPIOs
  target/mips: enable GINVx support for I6400 and I6500
  target/mips/mxu: Add Q8SAD instruction
  target/mips/mxu: Add S32SFL instruction
  target/mips/mxu: Add Q8MADL instruction
  target/mips/mxu: Add Q16SCOP instruction
  target/mips/mxu: Add Q8MAC Q8MACSU instructions
  target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions
  target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions
  target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions
  target/mips/mxu: Add D32SLL D32SLR D32SAR instructions
  target/mips/mxu: Add D32SARL D32SARW instructions
  target/mips/mxu: Add S32ALN S32LUI insns
  target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-07-11 07:36:33 +01:00
parent adc97c4b80 752dfff5ec
commit 154e3b61ac
25 changed files with 4001 additions and 162 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/ide/cmd646.c
View File

@ -144,7 +144,7 @@ static void bmdma_write(void *opaque, hwaddr addr,
cmd646_update_irq(pci_dev);
break;
case 2:
bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
bmdma_status_writeb(bm, val);
break;
case 3:
if (bm == &bm->pci_dev->bmdma[0]) {
@ -297,7 +297,6 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
}
}

16
hw/ide/pci.c
View File

@ -318,6 +318,12 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
bm->cmd = val & 0x09;
}
void bmdma_status_writeb(BMDMAState *bm, uint32_t val)
{
bm->status = (val & 0x60) | (bm->status & BM_STATUS_DMAING)
| (bm->status & ~val & (BM_STATUS_ERROR | BM_STATUS_INT));
}
static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
unsigned width)
{
@ -519,13 +525,23 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
bus->dma = &bm->dma;
bm->irq = bus->irq;
bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
bm->bus = bus;
bm->pci_dev = d;
}
static void pci_ide_init(Object *obj)
{
PCIIDEState *d = PCI_IDE(obj);
qdev_init_gpio_out_named(DEVICE(d), d->isa_irq, "isa-irq",
ARRAY_SIZE(d->isa_irq));
}
static const TypeInfo pci_ide_type_info = {
.name = TYPE_PCI_IDE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIIDEState),
.instance_init = pci_ide_init,
.abstract = true,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },

8
hw/ide/piix.c
View File

@ -28,7 +28,6 @@
*/
#include "qemu/osdep.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "hw/pci/pci.h"
#include "hw/ide/piix.h"
@ -76,7 +75,7 @@ static void bmdma_write(void *opaque, hwaddr addr,
bmdma_cmd_writeb(bm, val);
break;
case 2:
bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
bmdma_status_writeb(bm, val);
break;
}
}
@ -144,7 +143,6 @@ static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
return true;
@ -160,8 +158,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
bmdma_setup_bar(d);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
for (unsigned i = 0; i < 2; i++) {
if (!pci_piix_init_bus(d, i, errp)) {
return;
@ -187,6 +183,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->reset = piix_ide_reset;
dc->vmsd = &vmstate_ide_pci;
k->realize = pci_piix_ide_realize;
k->exit = pci_piix_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_INTEL;
@ -209,6 +206,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->reset = piix_ide_reset;
dc->vmsd = &vmstate_ide_pci;
k->realize = pci_piix_ide_realize;
k->exit = pci_piix_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_INTEL;

7
hw/ide/sii3112.c
View File

@ -149,8 +149,7 @@ static void sii3112_reg_write(void *opaque, hwaddr addr,
break;
case 0x02:
case 0x12:
d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) |
(d->i.bmdma[0].status & ~val & 6);
bmdma_status_writeb(&d->i.bmdma[0], val);
break;
case 0x04 ... 0x07:
bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size);
@ -165,8 +164,7 @@ static void sii3112_reg_write(void *opaque, hwaddr addr,
break;
case 0x0a:
case 0x1a:
d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) |
(d->i.bmdma[1].status & ~val & 6);
bmdma_status_writeb(&d->i.bmdma[1], val);
break;
case 0x0c ... 0x0f:
bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);
@ -287,7 +285,6 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&s->bus[i], &s->bmdma[i], s);
s->bmdma[i].bus = &s->bus[i];
ide_bus_register_restart_cb(&s->bus[i]);
}
}

9
hw/ide/via.c
View File

@ -31,6 +31,7 @@
#include "sysemu/dma.h"
#include "hw/isa/vt82c686.h"
#include "hw/ide/pci.h"
#include "hw/irq.h"
#include "trace.h"
static uint64_t bmdma_read(void *opaque, hwaddr addr,
@ -74,7 +75,7 @@ static void bmdma_write(void *opaque, hwaddr addr,
bmdma_cmd_writeb(bm, val);
break;
case 2:
bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
bmdma_status_writeb(bm, val);
break;
default:;
}
@ -104,7 +105,8 @@ static void bmdma_setup_bar(PCIIDEState *d)
static void via_ide_set_irq(void *opaque, int n, int level)
{
PCIDevice *d = PCI_DEVICE(opaque);
PCIIDEState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
if (level) {
d->config[0x70 + n * 8] |= 0x80;
@ -112,7 +114,7 @@ static void via_ide_set_irq(void *opaque, int n, int level)
d->config[0x70 + n * 8] &= ~0x80;
}
via_isa_set_irq(pci_get_function_0(d), 14 + n, level);
qemu_set_irq(s->isa_irq[n], level);
}
static void via_ide_reset(DeviceState *dev)
@ -194,7 +196,6 @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
}
}

11
hw/isa/vt82c686.c
View File

@ -592,12 +592,6 @@ static const TypeInfo via_isa_info = {
},
};
void via_isa_set_irq(PCIDevice *d, int n, int level)
{
ViaISAState *s = VIA_ISA(d);
qemu_set_irq(s->isa_irqs_in[n], level);
}
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
ViaISAState *s = opaque;
@ -692,6 +686,10 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
return;
}
for (i = 0; i < 2; i++) {
qdev_connect_gpio_out_named(DEVICE(&s->ide), "isa-irq", i,
s->isa_irqs_in[14 + i]);
}
/* Functions 2-3: USB Ports */
for (i = 0; i < ARRAY_SIZE(s->uhci); i++) {
@ -814,6 +812,7 @@ static void vt8231_isa_reset(DeviceState *dev)
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
pci_conf[0x4c] = 0x04; /* IDE interrupt Routing */
pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */
pci_conf[0x67] = 0x08; /* Fast IR Config */
pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */

4
hw/mips/loongson3_virt.c
View File

@ -481,8 +481,8 @@ static void mips_loongson3_virt_init(MachineState *machine)
if (!machine->cpu_type) {
machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
}
if (!strstr(machine->cpu_type, "Loongson-3A1000")) {
error_report("Loongson-3/TCG needs cpu type Loongson-3A1000");
if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) {
error_report("Loongson-3/TCG needs a Loongson-3 series cpu");
exit(1);
}
} else {

1
include/hw/ide/pci.h
View File

@ -58,6 +58,7 @@ struct PCIIDEState {
void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);
void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val);
void bmdma_status_writeb(BMDMAState *bm, uint32_t val);
extern MemoryRegionOps bmdma_addr_ioport_ops;
void pci_ide_create_devs(PCIDevice *dev);

2
include/hw/isa/vt82c686.h
View File

@ -34,6 +34,4 @@ struct ViaAC97State {
uint32_t ac97_cmd;
};
void via_isa_set_irq(PCIDevice *d, int n, int level);
#endif

59
target/mips/cpu-defs.c.inc
View File

@ -117,6 +117,26 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R1,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "XBurstR1",
.CP0_PRid = 0x1ed0024f,
.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(0 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3,
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R1 | ASE_MXU,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "4KEmR1",
.CP0_PRid = 0x00018500,
@ -323,6 +343,32 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "XBurstR2",
.CP0_PRid = 0x2ed1024f,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
(MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
(1 << CP0C3_VInt),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x3778FF1F,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R2 | ASE_MXU,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "M14K",
.CP0_PRid = 0x00019b00,
@ -709,7 +755,7 @@ const mips_def_t mips_defs[] =
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
(1 << CP0C5_LLB) | (1 << CP0C5_MRP),
(1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,
@ -749,7 +795,7 @@ const mips_def_t mips_defs[] =
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
(1 << CP0C5_LLB) | (1 << CP0C5_MRP),
(1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,
@ -895,6 +941,15 @@ const mips_def_t mips_defs[] =
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
.lcsr_cpucfg1 = (1 << CPUCFG1_FP) | (2 << CPUCFG1_FPREV) |
(1 << CPUCFG1_MSA1) | (1 << CPUCFG1_LSLDR0) |
(1 << CPUCFG1_LSPERF) | (1 << CPUCFG1_LSPERFX) |
(1 << CPUCFG1_LSSYNCI) | (1 << CPUCFG1_LLEXC) |
(1 << CPUCFG1_SCRAND) | (1 << CPUCFG1_MUALP) |
(1 << CPUCFG1_KMUALEN) | (1 << CPUCFG1_ITLBT) |
(1 << CPUCFG1_SFBP) | (1 << CPUCFG1_CDMAP),
.lcsr_cpucfg2 = (1 << CPUCFG2_LEXT1) | (1 << CPUCFG2_LCSRP) |
(1 << CPUCFG2_LDISBLIKELY),
.SEGBITS = 48,
.PABITS = 48,
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |

18
target/mips/cpu.c
View File

@ -244,6 +244,8 @@ static void mips_cpu_reset_hold(Object *obj)
env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
env->lcsr_cpucfg1 = env->cpu_model->lcsr_cpucfg1;
env->lcsr_cpucfg2 = env->cpu_model->lcsr_cpucfg2;
env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
@ -449,9 +451,9 @@ static void mips_cp0_period_set(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
env->cpu_model->CCRes);
assert(env->cp0_count_ns);
clock_set_mul_div(cpu->count_div, env->cpu_model->CCRes, 1);
clock_set_source(cpu->count_div, cpu->clock);
clock_set_source(env->count_clock, cpu->count_div);
}
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
@ -504,7 +506,17 @@ static void mips_cpu_initfn(Object *obj)
cpu_set_cpustate_pointers(cpu);
cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
cpu->count_div = clock_new(OBJECT(obj), "clk-div-count");
env->count_clock = clock_new(OBJECT(obj), "clk-count");
env->cpu_model = mcc->cpu_def;
#ifndef CONFIG_USER_ONLY
if (mcc->cpu_def->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP)) {
memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL,
env, "iocsr", UINT64_MAX);
address_space_init(&env->iocsr.as,
&env->iocsr.mr, "IOCSR");
}
#endif
}
static char *mips_cpu_type_name(const char *cpu_model)

45
target/mips/cpu.h
View File

@ -3,6 +3,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#ifndef CONFIG_USER_ONLY
#include "exec/memory.h"
#endif
#include "fpu/softfloat-types.h"
#include "hw/clock.h"
#include "mips-defs.h"
@ -1068,6 +1071,33 @@ typedef struct CPUArchState {
*/
int32_t CP0_DESAVE;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
/*
* Loongson CSR CPUCFG registers
*/
uint32_t lcsr_cpucfg1;
#define CPUCFG1_FP 0
#define CPUCFG1_FPREV 1
#define CPUCFG1_MMI 4
#define CPUCFG1_MSA1 5
#define CPUCFG1_MSA2 6
#define CPUCFG1_LSLDR0 16
#define CPUCFG1_LSPERF 17
#define CPUCFG1_LSPERFX 18
#define CPUCFG1_LSSYNCI 19
#define CPUCFG1_LLEXC 20
#define CPUCFG1_SCRAND 21
#define CPUCFG1_MUALP 25
#define CPUCFG1_KMUALEN 26
#define CPUCFG1_ITLBT 27
#define CPUCFG1_SFBP 29
#define CPUCFG1_CDMAP 30
uint32_t lcsr_cpucfg2;
#define CPUCFG2_LEXT1 0
#define CPUCFG2_LEXT2 1
#define CPUCFG2_LEXT3 2
#define CPUCFG2_LSPW 3
#define CPUCFG2_LCSRP 27
#define CPUCFG2_LDISBLIKELY 28
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
@ -1156,12 +1186,18 @@ typedef struct CPUArchState {
void *irq[8];
struct MIPSITUState *itu;
MemoryRegion *itc_tag; /* ITC Configuration Tags */
/* Loongson IOCSR memory */
struct {
AddressSpace as;
MemoryRegion mr;
} iocsr;
#endif
const mips_def_t *cpu_model;
QEMUTimer *timer; /* Internal timer */
Clock *count_clock; /* CP0_Count clock */
target_ulong exception_base; /* ExceptionBase input to the core */
uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */
} CPUMIPSState;
/**
@ -1178,6 +1214,7 @@ struct ArchCPU {
/*< public >*/
Clock *clock;
Clock *count_div; /* Divider for CP0_Count clock */
CPUNegativeOffsetState neg;
CPUMIPSState env;
};
@ -1280,6 +1317,12 @@ static inline bool ase_msa_available(CPUMIPSState *env)
return env->CP0_Config3 & (1 << CP0C3_MSAP);
}
/* Check presence of Loongson CSR instructions */
static inline bool ase_lcsr_available(CPUMIPSState *env)
{
return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP);
}
/* Check presence of multi-threading ASE implementation */
static inline bool ase_mt_available(CPUMIPSState *env)
{

4
target/mips/helper.h
View File

@ -196,6 +196,10 @@ DEF_HELPER_1(rdhwr_xnp, tl, env)
DEF_HELPER_2(pmon, void, env, int)
DEF_HELPER_1(wait, void, env)
#ifdef TARGET_MIPS64
DEF_HELPER_FLAGS_2(lcsr_cpucfg, TCG_CALL_NO_RWG_SE, tl, env, tl)
#endif
/* Loongson multimedia functions. */
DEF_HELPER_FLAGS_2(paddsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(paddush, TCG_CALL_NO_RWG_SE, i64, i64, i64)

2
target/mips/internal.h
View File

@ -79,6 +79,8 @@ struct mips_def_t {
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
target_ulong CP0_EBaseWG_rw_bitmask;
uint32_t lcsr_cpucfg1;
uint32_t lcsr_cpucfg2;
uint64_t insn_flags;
enum mips_mmu_types mmu_type;
int32_t SAARP;

35
target/mips/sysemu/cp0_timer.c
View File

@ -28,15 +28,26 @@
#include "internal.h"
/* MIPS R4K timer */
static uint32_t cpu_mips_get_count_val(CPUMIPSState *env)
{
int64_t now_ns;
now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
return env->CP0_Count +
(uint32_t)clock_ns_to_ticks(env->count_clock, now_ns);
}
static void cpu_mips_timer_update(CPUMIPSState *env)
{
uint64_t now_ns, next_ns;
uint32_t wait;
now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
wait = env->CP0_Compare - env->CP0_Count -
(uint32_t)(now_ns / env->cp0_count_ns);
next_ns = now_ns + (uint64_t)wait * env->cp0_count_ns;
wait = env->CP0_Compare - cpu_mips_get_count_val(env);
/* Clamp interval to overflow if virtual time had not progressed */
if (!wait) {
wait = UINT32_MAX;
}
next_ns = now_ns + clock_ticks_to_ns(env->count_clock, wait);
timer_mod(env->timer, next_ns);
}
@ -64,7 +75,7 @@ uint32_t cpu_mips_get_count(CPUMIPSState *env)
cpu_mips_timer_expire(env);
}
return env->CP0_Count + (uint32_t)(now_ns / env->cp0_count_ns);
return cpu_mips_get_count_val(env);
}
}
@ -79,9 +90,8 @@ void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
env->CP0_Count = count;
} else {
/* Store new count register */
env->CP0_Count = count -
(uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
env->cp0_count_ns);
env->CP0_Count = count - (uint32_t)clock_ns_to_ticks(env->count_clock,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
/* Update timer timer */
cpu_mips_timer_update(env);
}
@ -107,8 +117,8 @@ void cpu_mips_start_count(CPUMIPSState *env)
void cpu_mips_stop_count(CPUMIPSState *env)
{
/* Store the current value */
env->CP0_Count += (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
env->cp0_count_ns);
env->CP0_Count += (uint32_t)clock_ns_to_ticks(env->count_clock,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
static void mips_timer_cb(void *opaque)
@ -121,14 +131,7 @@ static void mips_timer_cb(void *opaque)
return;
}
/*
* ??? This callback should occur when the counter is exactly equal to
* the comparator value. Offset the count by one to avoid immediately
* retriggering the callback before any virtual time has passed.
*/
env->CP0_Count++;
cpu_mips_timer_expire(env);
env->CP0_Count--;
}
void cpu_mips_clock_init(MIPSCPU *cpu)

17
target/mips/tcg/lcsr.decode Normal file
View File

@ -0,0 +1,17 @@
# Loongson CSR instructions
#
# Copyright (C) 2023 Jiaxun Yang <jiaxun.yang@flygoat.com>
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
&r rs rt rd sa
@rs_rd ...... rs:5 ..... rd:5 ..... ...... &r rt=0 sa=0
CPUCFG 110010 ..... 01000 ..... 00100 011000 @rs_rd
RDCSR 110010 ..... 00000 ..... 00100 011000 @rs_rd
WRCSR 110010 ..... 00001 ..... 00100 011000 @rs_rd
DRDCSR 110010 ..... 00010 ..... 00100 011000 @rs_rd
DWRCSR 110010 ..... 00011 ..... 00100 011000 @rs_rd

75
target/mips/tcg/lcsr_translate.c Normal file
View File

@ -0,0 +1,75 @@
/*
* Loongson CSR instructions translation routines
*
* Copyright (c) 2023 Jiaxun Yang <jiaxun.yang@flygoat.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
#include "exec/helper-gen.h"
#include "translate.h"
/* Include the auto-generated decoder. */
#include "decode-lcsr.c.inc"
static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a)
{
TCGv dest = tcg_temp_new();
TCGv src1 = tcg_temp_new();
gen_load_gpr(src1, a->rs);
gen_helper_lcsr_cpucfg(dest, cpu_env, src1);
gen_store_gpr(dest, a->rd);
return true;
}
#ifndef CONFIG_USER_ONLY
static bool gen_rdcsr(DisasContext *ctx, arg_r *a,
void (*func)(TCGv, TCGv_ptr, TCGv))
{
TCGv dest = tcg_temp_new();
TCGv src1 = tcg_temp_new();
check_cp0_enabled(ctx);
gen_load_gpr(src1, a->rs);
func(dest, cpu_env, src1);
gen_store_gpr(dest, a->rd);
return true;
}
static bool gen_wrcsr(DisasContext *ctx, arg_r *a,
void (*func)(TCGv_ptr, TCGv, TCGv))
{
TCGv val = tcg_temp_new();
TCGv addr = tcg_temp_new();
check_cp0_enabled(ctx);
gen_load_gpr(addr, a->rs);
gen_load_gpr(val, a->rd);
func(cpu_env, addr, val);
return true;
}
TRANS(RDCSR, gen_rdcsr, gen_helper_lcsr_rdcsr)
TRANS(DRDCSR, gen_rdcsr, gen_helper_lcsr_drdcsr)
TRANS(WRCSR, gen_wrcsr, gen_helper_lcsr_wrcsr)
TRANS(DWRCSR, gen_wrcsr, gen_helper_lcsr_dwrcsr)
#else
#define GEN_FALSE_TRANS(name) \
static bool trans_##name(DisasContext *ctx, arg_##name * a) \
{ \
return false; \
}
GEN_FALSE_TRANS(RDCSR)
GEN_FALSE_TRANS(DRDCSR)
GEN_FALSE_TRANS(WRCSR)
GEN_FALSE_TRANS(DWRCSR)
#endif

2
target/mips/tcg/meson.build
View File

@ -4,6 +4,7 @@ gen = [
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'),
decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'),
decodetree.process('lcsr.decode', extra_args: '--decode=decode_ase_lcsr'),
]
mips_ss.add(gen)
@ -26,6 +27,7 @@ mips_ss.add(files(
mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
'tx79_translate.c',
'octeon_translate.c',
'lcsr_translate.c',
), if_false: files(
'mxu_translate.c',
))

3761
target/mips/tcg/mxu_translate.c
View File

File diff suppressed because it is too large Load Diff

16
target/mips/tcg/op_helper.c
View File

@ -257,6 +257,22 @@ void helper_pmon(CPUMIPSState *env, int function)
}
}
#ifdef TARGET_MIPS64
target_ulong helper_lcsr_cpucfg(CPUMIPSState *env, target_ulong rs)
{
switch (rs) {
case 0:
return env->CP0_PRid;
case 1:
return env->lcsr_cpucfg1;
case 2:
return env->lcsr_cpucfg2;
default:
return 0;
}
}
#endif
#if !defined(CONFIG_USER_ONLY)
void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

45
target/mips/tcg/sysemu/lcsr_helper.c Normal file
View File

@ -0,0 +1,45 @@
/*
* Loongson CSR instructions translation routines
*
* Copyright (c) 2023 Jiaxun Yang <jiaxun.yang@flygoat.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "internal.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#define GET_MEMTXATTRS(cas) \
((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
uint64_t helper_lcsr_rdcsr(CPUMIPSState *env, target_ulong r_addr)
{
return address_space_ldl(&env->iocsr.as, r_addr,
GET_MEMTXATTRS(env), NULL);
}
uint64_t helper_lcsr_drdcsr(CPUMIPSState *env, target_ulong r_addr)
{
return address_space_ldq(&env->iocsr.as, r_addr,
GET_MEMTXATTRS(env), NULL);
}
void helper_lcsr_wrcsr(CPUMIPSState *env, target_ulong w_addr,
target_ulong val)
{
address_space_stl(&env->iocsr.as, w_addr,
val, GET_MEMTXATTRS(env), NULL);
}
void helper_lcsr_dwrcsr(CPUMIPSState *env, target_ulong w_addr,
target_ulong val)
{
address_space_stq(&env->iocsr.as, w_addr,
val, GET_MEMTXATTRS(env), NULL);
}

4
target/mips/tcg/sysemu/meson.build
View File

@ -4,3 +4,7 @@ mips_system_ss.add(files(
'special_helper.c',
'tlb_helper.c',
))
mips_system_ss.add(when: 'TARGET_MIPS64', if_true: files(
'lcsr_helper.c',
))

8
target/mips/tcg/sysemu_helper.h.inc
View File

@ -181,3 +181,11 @@ DEF_HELPER_1(eret, void, env)
DEF_HELPER_1(eretnc, void, env)
DEF_HELPER_1(deret, void, env)
DEF_HELPER_3(cache, void, env, tl, i32)
#ifdef TARGET_MIPS64
/* Longson CSR */
DEF_HELPER_2(lcsr_rdcsr, i64, env, tl)
DEF_HELPER_2(lcsr_drdcsr, i64, env, tl)
DEF_HELPER_3(lcsr_wrcsr, void, env, tl, tl)
DEF_HELPER_3(lcsr_dwrcsr, void, env, tl, tl)
#endif

10
target/mips/tcg/translate.c
View File

@ -14644,12 +14644,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
}
#endif
if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) {
if (MASK_SPECIAL2(ctx->opcode) == OPC_MUL) {
gen_arith(ctx, OPC_MUL, rd, rs, rt);
} else {
decode_ase_mxu(ctx, ctx->opcode);
if (decode_ase_mxu(ctx, ctx->opcode)) {
break;
}
break;
}
decode_opc_special2_legacy(env, ctx);
break;
@ -15352,6 +15349,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
return;
}
#if defined(TARGET_MIPS64)
if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) {
return;
}
if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) {
return;
}

1
target/mips/tcg/translate.h
View File

@ -221,6 +221,7 @@ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
bool decode_ase_lcsr(DisasContext *ctx, uint32_t insn);
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
bool decode_ext_octeon(DisasContext *ctx, uint32_t insn);
#endif