target/arm: Mark up sysregs for HFGRTR bits 0..11
Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 0..11. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org
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@ -577,6 +577,20 @@ typedef enum FGTBit {
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FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
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FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
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FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
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/* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
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DO_BIT(HFGRTR, AFSR0_EL1),
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DO_BIT(HFGRTR, AFSR1_EL1),
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DO_BIT(HFGRTR, AIDR_EL1),
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DO_BIT(HFGRTR, AMAIR_EL1),
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DO_BIT(HFGRTR, APDAKEY),
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DO_BIT(HFGRTR, APDBKEY),
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DO_BIT(HFGRTR, APGAKEY),
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DO_BIT(HFGRTR, APIAKEY),
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DO_BIT(HFGRTR, APIBKEY),
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DO_BIT(HFGRTR, CCSIDR_EL1),
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DO_BIT(HFGRTR, CLIDR_EL1),
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DO_BIT(HFGRTR, CONTEXTIDR_EL1),
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} FGTBit;
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#undef DO_BIT
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@ -633,6 +633,7 @@ static const ARMCPRegInfo cp_reginfo[] = {
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{ .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fgt = FGT_CONTEXTIDR_EL1,
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.secure = ARM_CP_SECSTATE_NS,
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.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
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.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
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@ -2163,6 +2164,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
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.access = PL1_R,
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.accessfn = access_tid4,
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.fgt = FGT_CCSIDR_EL1,
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.readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
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{ .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
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@ -2179,6 +2181,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa64_tid1,
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.fgt = FGT_AIDR_EL1,
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.resetvalue = 0 },
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/*
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* Auxiliary fault status registers: these also are IMPDEF, and we
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@ -2187,10 +2190,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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{ .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fgt = FGT_AFSR0_EL1,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fgt = FGT_AFSR1_EL1,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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/*
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* MAIR can just read-as-written because we don't implement caches
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@ -4392,6 +4397,7 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
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{ .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fgt = FGT_AMAIR_EL1,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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/* AMAIR1 is mapped to AMAIR_EL1[63:32] */
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{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
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@ -7041,42 +7047,52 @@ static const ARMCPRegInfo pauth_reginfo[] = {
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{ .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APDAKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
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{ .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APDAKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
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{ .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APDBKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
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{ .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APDBKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
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{ .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APGAKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
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{ .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APGAKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
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{ .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APIAKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
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{ .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APIAKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
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{ .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APIBKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
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{ .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
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.access = PL1_RW, .accessfn = access_pauth,
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.fgt = FGT_APIBKEY,
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.fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
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};
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@ -7940,6 +7956,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_tid4,
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.fgt = FGT_CLIDR_EL1,
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.resetvalue = cpu->clidr
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};
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define_one_arm_cp_reg(cpu, &clidr);
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