OpenE2K/qemu-e2k
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* HAX support for Linux hosts (Alejandro)

Browse Source 
* esp bugfixes (Guenter)
 * Windows build cleanup (Marc-André)
 * checkpatch logic improvements (Paolo)
 * coalesced range bugfix (Paolo)
 * switch testsuite to TAP (Paolo)
 * QTAILQ rewrite (Paolo)
 * block/iscsi.c cancellation fixes (Stefan)
 * improve selection of the default accelerator (Thomas)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
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 =i8E5
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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* HAX support for Linux hosts (Alejandro)
* esp bugfixes (Guenter)
* Windows build cleanup (Marc-André)
* checkpatch logic improvements (Paolo)
* coalesced range bugfix (Paolo)
* switch testsuite to TAP (Paolo)
* QTAILQ rewrite (Paolo)
* block/iscsi.c cancellation fixes (Stefan)
* improve selection of the default accelerator (Thomas)

# gpg: Signature made Fri 11 Jan 2019 14:47:40 GMT
# gpg:                using RSA key BFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream: (34 commits)
  avoid TABs in files that only contain a few
  remove space-tab sequences
  scripts: add script to convert multiline comments into 4-line format
  hw/watchdog/wdt_i6300esb: remove a unnecessary comment
  checkpatch: warn about qemu/queue.h head structs that are not typedef-ed
  qemu/queue.h: simplify reverse access to QTAILQ
  qemu/queue.h: reimplement QTAILQ without pointer-to-pointers
  qemu/queue.h: remove Q_TAILQ_{HEAD,ENTRY}
  qemu/queue.h: typedef QTAILQ heads
  qemu/queue.h: leave head structs anonymous unless necessary
  vfio: make vfio_address_spaces static
  qemu/queue.h: do not access tqe_prev directly
  test: replace gtester with a TAP driver
  test: execute g_test_run when tests are skipped
  qga: drop < Vista compatibility
  build-sys: build with Vista API by default
  build-sys: move windows defines in osdep.h header
  build-sys: don't include windows.h, osdep.h does it
  scsi: esp: Defer command completion until previous interrupts have been handled
  esp-pci: Fix status register write erase control
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-01-11 15:46:09 +00:00
commit 15bede5541
207 changed files with 1498 additions and 897 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
accel/accel.c
View File

@ -69,7 +69,7 @@ static int accel_init_machine(AccelClass *acc, MachineState *ms)
return ret;
}
void configure_accelerator(MachineState *ms)
void configure_accelerator(MachineState *ms, const char *progname)
{
const char *accel;
char **accel_list, **tmp;
@ -80,8 +80,20 @@ void configure_accelerator(MachineState *ms)
accel = qemu_opt_get(qemu_get_machine_opts(), "accel");
if (accel == NULL) {
/* Use the default "accelerator", tcg */
accel = "tcg";
/* Select the default accelerator */
int pnlen = strlen(progname);
if (pnlen >= 3 && g_str_equal(&progname[pnlen - 3], "kvm")) {
/* If the program name ends with "kvm", we prefer KVM */
accel = "kvm:tcg";
} else {
#if defined(CONFIG_TCG)
accel = "tcg";
#elif defined(CONFIG_KVM)
accel = "kvm";
#else
#error "No default accelerator available"
#endif
}
}
accel_list = g_strsplit(accel, ":", 0);

4
accel/kvm/kvm-all.c
View File

@ -86,7 +86,7 @@ struct KVMState
int robust_singlestep;
int debugregs;
#ifdef KVM_CAP_SET_GUEST_DEBUG
struct kvm_sw_breakpoint_head kvm_sw_breakpoints;
QTAILQ_HEAD(, kvm_sw_breakpoint) kvm_sw_breakpoints;
#endif
int many_ioeventfds;
int intx_set_mask;
@ -102,7 +102,7 @@ struct KVMState
int nr_allocated_irq_routes;
unsigned long *used_gsi_bitmap;
unsigned int gsi_count;
QTAILQ_HEAD(msi_hashtab, KVMMSIRoute) msi_hashtab[KVM_MSI_HASHTAB_SIZE];
QTAILQ_HEAD(, KVMMSIRoute) msi_hashtab[KVM_MSI_HASHTAB_SIZE];
#endif
KVMMemoryListener memory_listener;
QLIST_HEAD(, KVMParkedVcpu) kvm_parked_vcpus;

4
accel/tcg/translate-all.c
View File

@ -16,12 +16,8 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifdef _WIN32
#include <windows.h>
#endif
#include "qemu/osdep.h"
#include "qemu-common.h"
#define NO_CPU_IO_DEFS
#include "cpu.h"

22
block/bochs.c
View File

@ -85,14 +85,14 @@ static int bochs_probe(const uint8_t *buf, int buf_size, const char *filename)
const struct bochs_header *bochs = (const void *)buf;
if (buf_size < HEADER_SIZE)
return 0;
return 0;
if (!strcmp(bochs->magic, HEADER_MAGIC) &&
!strcmp(bochs->type, REDOLOG_TYPE) &&
!strcmp(bochs->subtype, GROWING_TYPE) &&
((le32_to_cpu(bochs->version) == HEADER_VERSION) ||
(le32_to_cpu(bochs->version) == HEADER_V1)))
return 100;
!strcmp(bochs->type, REDOLOG_TYPE) &&
!strcmp(bochs->subtype, GROWING_TYPE) &&
((le32_to_cpu(bochs->version) == HEADER_VERSION) ||
(le32_to_cpu(bochs->version) == HEADER_V1)))
return 100;
return 0;
}
@ -125,8 +125,8 @@ static int bochs_open(BlockDriverState *bs, QDict *options, int flags,
if (strcmp(bochs.magic, HEADER_MAGIC) ||
strcmp(bochs.type, REDOLOG_TYPE) ||
strcmp(bochs.subtype, GROWING_TYPE) ||
((le32_to_cpu(bochs.version) != HEADER_VERSION) &&
(le32_to_cpu(bochs.version) != HEADER_V1))) {
((le32_to_cpu(bochs.version) != HEADER_VERSION) &&
(le32_to_cpu(bochs.version) != HEADER_V1))) {
error_setg(errp, "Image not in Bochs format");
return -EINVAL;
}
@ -158,7 +158,7 @@ static int bochs_open(BlockDriverState *bs, QDict *options, int flags,
}
for (i = 0; i < s->catalog_size; i++)
le32_to_cpus(&s->catalog_bitmap[i]);
le32_to_cpus(&s->catalog_bitmap[i]);
s->data_offset = le32_to_cpu(bochs.header) + (s->catalog_size * 4);
@ -217,7 +217,7 @@ static int64_t seek_to_sector(BlockDriverState *bs, int64_t sector_num)
extent_offset = (offset % s->extent_size) / 512;
if (s->catalog_bitmap[extent_index] == 0xffffffff) {
return 0; /* not allocated */
return 0; /* not allocated */
}
bitmap_offset = s->data_offset +
@ -232,7 +232,7 @@ static int64_t seek_to_sector(BlockDriverState *bs, int64_t sector_num)
}
if (!((bitmap_entry >> (extent_offset % 8)) & 1)) {
return 0; /* not allocated */
return 0; /* not allocated */
}
return bitmap_offset + (512 * (s->bitmap_blocks + extent_offset));

2
block/file-posix.c
View File

@ -2083,7 +2083,7 @@ again:
#endif
if (!fstat(fd, &sb) && (S_IFCHR & sb.st_mode)) {
#ifdef DIOCGMEDIASIZE
if (ioctl(fd, DIOCGMEDIASIZE, (off_t *)&size))
if (ioctl(fd, DIOCGMEDIASIZE, (off_t *)&size))
#elif defined(DIOCGPART)
{
struct partinfo pi;

8
block/file-win32.c
View File

@ -176,7 +176,7 @@ int qemu_ftruncate64(int fd, int64_t length)
BOOL res;
if ((GetVersion() & 0x80000000UL) && (length >> 32) != 0)
return -1;
return -1;
h = (HANDLE)_get_osfhandle(fd);
@ -184,13 +184,13 @@ int qemu_ftruncate64(int fd, int64_t length)
li.HighPart = 0;
li.LowPart = SetFilePointer (h, 0, &li.HighPart, FILE_CURRENT);
if (li.LowPart == INVALID_SET_FILE_POINTER && GetLastError() != NO_ERROR) {
return -1;
return -1;
}
high = length >> 32;
dw = SetFilePointer(h, (DWORD) length, &high, FILE_BEGIN);
if (dw == INVALID_SET_FILE_POINTER && GetLastError() != NO_ERROR) {
return -1;
return -1;
}
res = SetEndOfFile(h);
@ -203,7 +203,7 @@ static int set_sparse(int fd)
{
DWORD returned;
return (int) DeviceIoControl((HANDLE)_get_osfhandle(fd), FSCTL_SET_SPARSE,
NULL, 0, NULL, 0, &returned, NULL);
NULL, 0, NULL, 0, &returned, NULL);
}
static void raw_detach_aio_context(BlockDriverState *bs)

2
block/gluster.c
View File

@ -72,7 +72,7 @@ typedef struct ListElement {
GlfsPreopened saved;
} ListElement;
static QLIST_HEAD(glfs_list, ListElement) glfs_list;
static QLIST_HEAD(, ListElement) glfs_list;
static QemuOptsList qemu_gluster_create_opts = {
.name = "qemu-gluster-create-opts",

49
block/iscsi.c
View File

@ -117,7 +117,6 @@ typedef struct IscsiAIOCB {
QEMUBH *bh;
IscsiLun *iscsilun;
struct scsi_task *task;
uint8_t *buf;
int status;
int64_t sector_num;
int nb_sectors;
@ -125,6 +124,7 @@ typedef struct IscsiAIOCB {
#ifdef __linux__
sg_io_hdr_t *ioh;
#endif
bool cancelled;
} IscsiAIOCB;
/* libiscsi uses time_t so its enough to process events every second */
@ -150,9 +150,6 @@ iscsi_bh_cb(void *p)
qemu_bh_delete(acb->bh);
g_free(acb->buf);
acb->buf = NULL;
acb->common.cb(acb->common.opaque, acb->status);
if (acb->task != NULL) {
@ -291,14 +288,20 @@ static void iscsi_co_init_iscsitask(IscsiLun *iscsilun, struct IscsiTask *iTask)
};
}
/* Called (via iscsi_service) with QemuMutex held. */
static void
iscsi_abort_task_cb(struct iscsi_context *iscsi, int status, void *command_data,
void *private_data)
{
IscsiAIOCB *acb = private_data;
acb->status = -ECANCELED;
iscsi_schedule_bh(acb);
/* If the command callback hasn't been called yet, drop the task */
if (!acb->bh) {
/* Call iscsi_aio_ioctl_cb() with SCSI_STATUS_CANCELLED */
iscsi_scsi_cancel_task(iscsi, acb->task);
}
qemu_aio_unref(acb); /* acquired in iscsi_aio_cancel() */
}
static void
@ -307,14 +310,25 @@ iscsi_aio_cancel(BlockAIOCB *blockacb)
IscsiAIOCB *acb = (IscsiAIOCB *)blockacb;
IscsiLun *iscsilun = acb->iscsilun;
if (acb->status != -EINPROGRESS) {
qemu_mutex_lock(&iscsilun->mutex);
/* If it was cancelled or completed already, our work is done here */
if (acb->cancelled || acb->status != -EINPROGRESS) {
qemu_mutex_unlock(&iscsilun->mutex);
return;
}
/* send a task mgmt call to the target to cancel the task on the target */
iscsi_task_mgmt_abort_task_async(iscsilun->iscsi, acb->task,
iscsi_abort_task_cb, acb);
acb->cancelled = true;
qemu_aio_ref(acb); /* released in iscsi_abort_task_cb() */
/* send a task mgmt call to the target to cancel the task on the target */
if (iscsi_task_mgmt_abort_task_async(iscsilun->iscsi, acb->task,
iscsi_abort_task_cb, acb) < 0) {
qemu_aio_unref(acb); /* since iscsi_abort_task_cb() won't be called */
}
qemu_mutex_unlock(&iscsilun->mutex);
}
static const AIOCBInfo iscsi_aiocb_info = {
@ -348,6 +362,8 @@ static void iscsi_timed_check_events(void *opaque)
{
IscsiLun *iscsilun = opaque;
qemu_mutex_lock(&iscsilun->mutex);
/* check for timed out requests */
iscsi_service(iscsilun->iscsi, 0);
@ -360,6 +376,8 @@ static void iscsi_timed_check_events(void *opaque)
* to return to service once this situation changes. */
iscsi_set_events(iscsilun);
qemu_mutex_unlock(&iscsilun->mutex);
timer_mod(iscsilun->event_timer,
qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + EVENT_INTERVAL);
}
@ -933,8 +951,13 @@ iscsi_aio_ioctl_cb(struct iscsi_context *iscsi, int status,
{
IscsiAIOCB *acb = opaque;
g_free(acb->buf);
acb->buf = NULL;
if (status == SCSI_STATUS_CANCELLED) {
if (!acb->bh) {
acb->status = -ECANCELED;
iscsi_schedule_bh(acb);
}
return;
}
acb->status = 0;
if (status < 0) {
@ -1010,8 +1033,8 @@ static BlockAIOCB *iscsi_aio_ioctl(BlockDriverState *bs,
acb->iscsilun = iscsilun;
acb->bh = NULL;
acb->status = -EINPROGRESS;
acb->buf = NULL;
acb->ioh = buf;
acb->cancelled = false;
if (req != SG_IO) {
iscsi_ioctl_handle_emulated(acb, req, buf);

4
block/linux-aio.c
View File

@ -384,10 +384,10 @@ static int laio_do_submit(int fd, struct qemu_laiocb *laiocb, off_t offset,
switch (type) {
case QEMU_AIO_WRITE:
io_prep_pwritev(iocbs, fd, qiov->iov, qiov->niov, offset);
break;
break;
case QEMU_AIO_READ:
io_prep_preadv(iocbs, fd, qiov->iov, qiov->niov, offset);
break;
break;
/* Currently Linux kernel does not support other operations */
default:
fprintf(stderr, "%s: invalid AIO request type 0x%x.\n",

2
block/mirror.c
View File

@ -72,7 +72,7 @@ typedef struct MirrorBlockJob {
unsigned long *in_flight_bitmap;
int in_flight;
int64_t bytes_in_flight;
QTAILQ_HEAD(MirrorOpList, MirrorOp) ops_in_flight;
QTAILQ_HEAD(, MirrorOp) ops_in_flight;
int ret;
bool unmap;
int target_cluster_size;

4
block/qcow2-bitmap.c
View File

@ -77,8 +77,6 @@ typedef struct Qcow2BitmapTable {
uint32_t size; /* number of 64bit entries */
QSIMPLEQ_ENTRY(Qcow2BitmapTable) entry;
} Qcow2BitmapTable;
typedef QSIMPLEQ_HEAD(Qcow2BitmapTableList, Qcow2BitmapTable)
Qcow2BitmapTableList;
typedef struct Qcow2Bitmap {
Qcow2BitmapTable table;
@ -1316,7 +1314,7 @@ void qcow2_store_persistent_dirty_bitmaps(BlockDriverState *bs, Error **errp)
int ret;
Qcow2BitmapList *bm_list;
Qcow2Bitmap *bm;
Qcow2BitmapTableList drop_tables;
QSIMPLEQ_HEAD(, Qcow2BitmapTable) drop_tables;
Qcow2BitmapTable *tb, *tb_next;
if (!bdrv_has_changed_persistent_bitmaps(bs)) {

2
block/qcow2-cluster.c
View File

@ -402,7 +402,7 @@ static int count_contiguous_clusters(int nb_clusters, int cluster_size,
}
}
return i;
return i;
}
/*

5
block/qcow2.h
View File

@ -278,7 +278,10 @@ typedef struct BDRVQcow2State {
QEMUTimer *cache_clean_timer;
unsigned cache_clean_interval;
QLIST_HEAD(QCowClusterAlloc, QCowL2Meta) cluster_allocs;
uint8_t *cluster_cache;
uint8_t *cluster_data;
uint64_t cluster_cache_offset;
QLIST_HEAD(, QCowL2Meta) cluster_allocs;
uint64_t *refcount_table;
uint64_t refcount_table_offset;

6
block/sheepdog.c
View File

@ -391,12 +391,12 @@ struct BDRVSheepdogState {
uint32_t aioreq_seq_num;
/* Every aio request must be linked to either of these queues. */
QLIST_HEAD(inflight_aio_head, AIOReq) inflight_aio_head;
QLIST_HEAD(failed_aio_head, AIOReq) failed_aio_head;
QLIST_HEAD(, AIOReq) inflight_aio_head;
QLIST_HEAD(, AIOReq) failed_aio_head;
CoMutex queue_lock;
CoQueue overlapping_queue;
QLIST_HEAD(inflight_aiocb_head, SheepdogAIOCB) inflight_aiocb_head;
QLIST_HEAD(, SheepdogAIOCB) inflight_aiocb_head;
};
typedef struct BDRVSheepdogReopenState {

2
block/vhdx.h
View File

@ -398,7 +398,7 @@ typedef struct BDRVVHDXState {
bool log_replayed_on_open;
QLIST_HEAD(VHDXRegionHead, VHDXRegionEntry) regions;
QLIST_HEAD(, VHDXRegionEntry) regions;
} BDRVVHDXState;
void vhdx_guid_generate(MSGUID *guid);

2
block/vpc.c
View File

@ -187,7 +187,7 @@ static uint32_t vpc_checksum(uint8_t* buf, size_t size)
static int vpc_probe(const uint8_t *buf, int buf_size, const char *filename)
{
if (buf_size >= 8 && !strncmp((char *)buf, "conectix", 8))
return 100;
return 100;
return 0;
}

4
blockdev.c
View File

@ -2266,7 +2266,7 @@ void qmp_transaction(TransactionActionList *dev_list,
BlkActionState *state, *next;
Error *local_err = NULL;
QSIMPLEQ_HEAD(snap_bdrv_states, BlkActionState) snap_bdrv_states;
QSIMPLEQ_HEAD(, BlkActionState) snap_bdrv_states;
QSIMPLEQ_INIT(&snap_bdrv_states);
/* Does this transaction get canceled as a group on failure?
@ -4252,7 +4252,7 @@ void qmp_blockdev_del(const char *node_name, Error **errp)
goto out;
}
if (!bs->monitor_list.tqe_prev) {
if (!QTAILQ_IN_USE(bs, monitor_list)) {
error_setg(errp, "Node %s is not owned by the monitor",
bs->node_name);
goto out;

2
bsd-user/elfload.c
View File

@ -1367,7 +1367,7 @@ int load_elf_binary(struct linux_binprm * bprm, struct target_pt_regs * regs,
if (!have_guest_base) {
/*
* Go through ELF program header table and find out whether
* any of the segments drop below our current mmap_min_addr and
* any of the segments drop below our current mmap_min_addr and
* in that case set guest_base to corresponding address.
*/
for (i = 0, elf_ppnt = elf_phdata; i < elf_ex.e_phnum;

2
bsd-user/x86_64/target_syscall.h
View File

@ -12,7 +12,7 @@ struct target_pt_regs {
abi_ulong rbp;
abi_ulong rbx;
/* arguments: non interrupts/non tracing syscalls only save up to here */
abi_ulong r11;
abi_ulong r11;
abi_ulong r10;
abi_ulong r9;
abi_ulong r8;

3
configure vendored
View File

@ -912,9 +912,6 @@ fi
if test "$mingw32" = "yes" ; then
EXESUF=".exe"
DSOSUF=".dll"
QEMU_CFLAGS="-DWIN32_LEAN_AND_MEAN -DWINVER=0x501 $QEMU_CFLAGS"
# enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later)
QEMU_CFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $QEMU_CFLAGS"
# MinGW needs -mthreads for TLS and macro _MT.
QEMU_CFLAGS="-mthreads $QEMU_CFLAGS"
LIBS="-lwinmm -lws2_32 -liphlpapi $LIBS"

2
contrib/elf2dmp/main.c
View File

@ -296,7 +296,7 @@ static int fill_header(WinDumpHeader64 *hdr, struct pa_space *ps,
static int fill_context(KDDEBUGGER_DATA64 *kdbg,
struct va_space *vs, QEMU_Elf *qe)
{
int i;
int i;
for (i = 0; i < qe->state_nr; i++) {
uint64_t Prcb;
uint64_t Context;

4
contrib/ivshmem-client/ivshmem-client.h
View File

@ -46,9 +46,7 @@ typedef struct IvshmemClientPeer {
int vectors[IVSHMEM_CLIENT_MAX_VECTORS]; /**< one fd per vector */
unsigned vectors_count; /**< number of vectors */
} IvshmemClientPeer;
QTAILQ_HEAD(IvshmemClientPeerList, IvshmemClientPeer);
typedef struct IvshmemClientPeerList IvshmemClientPeerList;
typedef struct IvshmemClient IvshmemClient;
/**
@ -73,7 +71,7 @@ struct IvshmemClient {
int sock_fd; /**< unix sock filedesc */
int shm_fd; /**< shm file descriptor */
IvshmemClientPeerList peer_list; /**< list of peers */
QTAILQ_HEAD(, IvshmemClientPeer) peer_list; /**< list of peers */
IvshmemClientPeer local; /**< our own infos */
IvshmemClientNotifCb notif_cb; /**< notification callback */

5
contrib/ivshmem-server/ivshmem-server.h
View File

@ -52,9 +52,6 @@ typedef struct IvshmemServerPeer {
EventNotifier vectors[IVSHMEM_SERVER_MAX_VECTORS]; /**< one per vector */
unsigned vectors_count; /**< number of vectors */
} IvshmemServerPeer;
QTAILQ_HEAD(IvshmemServerPeerList, IvshmemServerPeer);
typedef struct IvshmemServerPeerList IvshmemServerPeerList;
/**
* Structure describing an ivshmem server
@ -72,7 +69,7 @@ typedef struct IvshmemServer {
unsigned n_vectors; /**< number of vectors */
uint16_t cur_id; /**< id to be given to next client */
bool verbose; /**< true in verbose mode */
IvshmemServerPeerList peer_list; /**< list of peers */
QTAILQ_HEAD(, IvshmemServerPeer) peer_list; /**< list of peers */
} IvshmemServer;
/**

2
cpus-common.c
View File

@ -99,7 +99,7 @@ void cpu_list_remove(CPUState *cpu)
return;
}
assert(!(cpu_index_auto_assigned && cpu != QTAILQ_LAST(&cpus, CPUTailQ)));
assert(!(cpu_index_auto_assigned && cpu != QTAILQ_LAST(&cpus)));
QTAILQ_REMOVE_RCU(&cpus, cpu, node);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;

28
crypto/aes.c
View File

@ -1071,7 +1071,7 @@ int AES_set_encrypt_key(const unsigned char *userKey, const int bits,
AES_KEY *key) {
u32 *rk;
int i = 0;
int i = 0;
u32 temp;
if (!userKey || !key)
@ -1160,7 +1160,7 @@ int AES_set_encrypt_key(const unsigned char *userKey, const int bits,
rk[15] = rk[ 7] ^ rk[14];
rk += 8;
}
}
}
abort();
}
@ -1247,7 +1247,7 @@ void AES_encrypt(const unsigned char *in, unsigned char *out,
t1 = AES_Te0[s1 >> 24] ^ AES_Te1[(s2 >> 16) & 0xff] ^ AES_Te2[(s3 >> 8) & 0xff] ^ AES_Te3[s0 & 0xff] ^ rk[ 5];
t2 = AES_Te0[s2 >> 24] ^ AES_Te1[(s3 >> 16) & 0xff] ^ AES_Te2[(s0 >> 8) & 0xff] ^ AES_Te3[s1 & 0xff] ^ rk[ 6];
t3 = AES_Te0[s3 >> 24] ^ AES_Te1[(s0 >> 16) & 0xff] ^ AES_Te2[(s1 >> 8) & 0xff] ^ AES_Te3[s2 & 0xff] ^ rk[ 7];
/* round 2: */
/* round 2: */
s0 = AES_Te0[t0 >> 24] ^ AES_Te1[(t1 >> 16) & 0xff] ^ AES_Te2[(t2 >> 8) & 0xff] ^ AES_Te3[t3 & 0xff] ^ rk[ 8];
s1 = AES_Te0[t1 >> 24] ^ AES_Te1[(t2 >> 16) & 0xff] ^ AES_Te2[(t3 >> 8) & 0xff] ^ AES_Te3[t0 & 0xff] ^ rk[ 9];
s2 = AES_Te0[t2 >> 24] ^ AES_Te1[(t3 >> 16) & 0xff] ^ AES_Te2[(t0 >> 8) & 0xff] ^ AES_Te3[t1 & 0xff] ^ rk[10];
@ -1257,7 +1257,7 @@ void AES_encrypt(const unsigned char *in, unsigned char *out,
t1 = AES_Te0[s1 >> 24] ^ AES_Te1[(s2 >> 16) & 0xff] ^ AES_Te2[(s3 >> 8) & 0xff] ^ AES_Te3[s0 & 0xff] ^ rk[13];
t2 = AES_Te0[s2 >> 24] ^ AES_Te1[(s3 >> 16) & 0xff] ^ AES_Te2[(s0 >> 8) & 0xff] ^ AES_Te3[s1 & 0xff] ^ rk[14];
t3 = AES_Te0[s3 >> 24] ^ AES_Te1[(s0 >> 16) & 0xff] ^ AES_Te2[(s1 >> 8) & 0xff] ^ AES_Te3[s2 & 0xff] ^ rk[15];
/* round 4: */
/* round 4: */
s0 = AES_Te0[t0 >> 24] ^ AES_Te1[(t1 >> 16) & 0xff] ^ AES_Te2[(t2 >> 8) & 0xff] ^ AES_Te3[t3 & 0xff] ^ rk[16];
s1 = AES_Te0[t1 >> 24] ^ AES_Te1[(t2 >> 16) & 0xff] ^ AES_Te2[(t3 >> 8) & 0xff] ^ AES_Te3[t0 & 0xff] ^ rk[17];
s2 = AES_Te0[t2 >> 24] ^ AES_Te1[(t3 >> 16) & 0xff] ^ AES_Te2[(t0 >> 8) & 0xff] ^ AES_Te3[t1 & 0xff] ^ rk[18];
@ -1267,7 +1267,7 @@ void AES_encrypt(const unsigned char *in, unsigned char *out,
t1 = AES_Te0[s1 >> 24] ^ AES_Te1[(s2 >> 16) & 0xff] ^ AES_Te2[(s3 >> 8) & 0xff] ^ AES_Te3[s0 & 0xff] ^ rk[21];
t2 = AES_Te0[s2 >> 24] ^ AES_Te1[(s3 >> 16) & 0xff] ^ AES_Te2[(s0 >> 8) & 0xff] ^ AES_Te3[s1 & 0xff] ^ rk[22];
t3 = AES_Te0[s3 >> 24] ^ AES_Te1[(s0 >> 16) & 0xff] ^ AES_Te2[(s1 >> 8) & 0xff] ^ AES_Te3[s2 & 0xff] ^ rk[23];
/* round 6: */
/* round 6: */
s0 = AES_Te0[t0 >> 24] ^ AES_Te1[(t1 >> 16) & 0xff] ^ AES_Te2[(t2 >> 8) & 0xff] ^ AES_Te3[t3 & 0xff] ^ rk[24];
s1 = AES_Te0[t1 >> 24] ^ AES_Te1[(t2 >> 16) & 0xff] ^ AES_Te2[(t3 >> 8) & 0xff] ^ AES_Te3[t0 & 0xff] ^ rk[25];
s2 = AES_Te0[t2 >> 24] ^ AES_Te1[(t3 >> 16) & 0xff] ^ AES_Te2[(t0 >> 8) & 0xff] ^ AES_Te3[t1 & 0xff] ^ rk[26];
@ -1277,7 +1277,7 @@ void AES_encrypt(const unsigned char *in, unsigned char *out,
t1 = AES_Te0[s1 >> 24] ^ AES_Te1[(s2 >> 16) & 0xff] ^ AES_Te2[(s3 >> 8) & 0xff] ^ AES_Te3[s0 & 0xff] ^ rk[29];
t2 = AES_Te0[s2 >> 24] ^ AES_Te1[(s3 >> 16) & 0xff] ^ AES_Te2[(s0 >> 8) & 0xff] ^ AES_Te3[s1 & 0xff] ^ rk[30];
t3 = AES_Te0[s3 >> 24] ^ AES_Te1[(s0 >> 16) & 0xff] ^ AES_Te2[(s1 >> 8) & 0xff] ^ AES_Te3[s2 & 0xff] ^ rk[31];
/* round 8: */
/* round 8: */
s0 = AES_Te0[t0 >> 24] ^ AES_Te1[(t1 >> 16) & 0xff] ^ AES_Te2[(t2 >> 8) & 0xff] ^ AES_Te3[t3 & 0xff] ^ rk[32];
s1 = AES_Te0[t1 >> 24] ^ AES_Te1[(t2 >> 16) & 0xff] ^ AES_Te2[(t3 >> 8) & 0xff] ^ AES_Te3[t0 & 0xff] ^ rk[33];
s2 = AES_Te0[t2 >> 24] ^ AES_Te1[(t3 >> 16) & 0xff] ^ AES_Te2[(t0 >> 8) & 0xff] ^ AES_Te3[t1 & 0xff] ^ rk[34];
@ -1569,33 +1569,33 @@ void AES_decrypt(const unsigned char *in, unsigned char *out,
* apply last round and
* map cipher state to byte array block:
*/
s0 =
s0 =
(AES_Td4[(t0 >> 24) ] & 0xff000000) ^
(AES_Td4[(t3 >> 16) & 0xff] & 0x00ff0000) ^
(AES_Td4[(t2 >> 8) & 0xff] & 0x0000ff00) ^
(AES_Td4[(t1 ) & 0xff] & 0x000000ff) ^
rk[0];
rk[0];
PUTU32(out , s0);
s1 =
s1 =
(AES_Td4[(t1 >> 24) ] & 0xff000000) ^
(AES_Td4[(t0 >> 16) & 0xff] & 0x00ff0000) ^
(AES_Td4[(t3 >> 8) & 0xff] & 0x0000ff00) ^
(AES_Td4[(t2 ) & 0xff] & 0x000000ff) ^
rk[1];
rk[1];
PUTU32(out + 4, s1);
s2 =
s2 =
(AES_Td4[(t2 >> 24) ] & 0xff000000) ^
(AES_Td4[(t1 >> 16) & 0xff] & 0x00ff0000) ^
(AES_Td4[(t0 >> 8) & 0xff] & 0x0000ff00) ^
(AES_Td4[(t3 ) & 0xff] & 0x000000ff) ^
rk[2];
rk[2];
PUTU32(out + 8, s2);
s3 =
s3 =
(AES_Td4[(t3 >> 24) ] & 0xff000000) ^
(AES_Td4[(t2 >> 16) & 0xff] & 0x00ff0000) ^
(AES_Td4[(t1 >> 8) & 0xff] & 0x0000ff00) ^
(AES_Td4[(t0 ) & 0xff] & 0x000000ff) ^
rk[3];
rk[3];
PUTU32(out + 12, s3);
}

8
disas/alpha.c
View File

@ -672,7 +672,7 @@ extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
OPCODE is the instruction opcode.
MASK is the opcode mask; this is used to tell the disassembler
which bits in the actual opcode must match OPCODE.
which bits in the actual opcode must match OPCODE.
OPERANDS is the list of operands.
@ -699,10 +699,10 @@ extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
And two annotations:
EV56 BUT opcodes that are officially introduced as of the ev56,
but with defined results on previous implementations.
but with defined results on previous implementations.
EV56 UNA opcodes that were introduced as of the ev56 with
presumably undefined results on previous implementations
presumably undefined results on previous implementations
that were not assigned to a particular extension.
*/
@ -832,7 +832,7 @@ const struct alpha_opcode alpha_opcodes[] = {
{ "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR },
{ "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL },
{ "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
0xFFFFFFE0, BASE, { RC } }, /* ev56 but */
0xFFFFFFE0, BASE, { RC } }, /* ev56 but */
{ "mskbl", OPR(0x12,0x02), BASE, ARG_OPR },
{ "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL },

2
disas/arm.c
View File

@ -1077,7 +1077,7 @@ static const struct opcode32 arm_opcodes[] =
%S print Thumb register (bits 3..5 as high number if bit 6 set)
%D print Thumb register (bits 0..2 as high number if bit 7 set)
%<bitfield>I print bitfield as a signed decimal
(top bit of range being the sign bit)
(top bit of range being the sign bit)
%N print Thumb register mask (with LR)
%O print Thumb register mask (with PC)
%M print Thumb register mask

4
disas/i386.c
View File

@ -6075,7 +6075,7 @@ OP_EM (int bytemode, int sizeflag)
{
bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
used_prefixes |= (prefixes & PREFIX_DATA);
}
}
OP_E (bytemode, sizeflag);
return;
}
@ -6112,7 +6112,7 @@ OP_EMC (int bytemode, int sizeflag)
{
bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
used_prefixes |= (prefixes & PREFIX_DATA);
}
}
OP_E (bytemode, sizeflag);
return;
}

4
disas/m68k.c
View File

@ -350,7 +350,7 @@ struct m68k_opcode_alias
* all (modes 0-6,7.0-4)
~ alterable memory (modes 2-6,7.0,7.1)
(not 0,1,7.2-4)
(not 0,1,7.2-4)
% alterable (modes 0-6,7.0,7.1)
(not 7.2-4)
; data (modes 0,2-6,7.0-4)
@ -1647,7 +1647,7 @@ print_insn_arg (const char *d,
case 0x15: name = "%val"; break;
case 0x16: name = "%scc"; break;
case 0x17: name = "%ac"; break;
case 0x18: name = "%psr"; break;
case 0x18: name = "%psr"; break;
case 0x19: name = "%pcsr"; break;
case 0x1c:
case 0x1d:

2
dump.c
View File

@ -1557,7 +1557,7 @@ static void get_max_mapnr(DumpState *s)
{
GuestPhysBlock *last_block;
last_block = QTAILQ_LAST(&s->guest_phys_blocks.head, GuestPhysBlockHead);
last_block = QTAILQ_LAST(&s->guest_phys_blocks.head);
s->max_mapnr = dump_paddr_to_pfn(s, last_block->target_end);
}

5
exec.c
View File

@ -94,7 +94,8 @@ int target_page_bits;
bool target_page_bits_decided;
#endif
struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
/* current CPU in the current thread. It is only valid inside
cpu_exec() */
__thread CPUState *current_cpu;
@ -3471,7 +3472,7 @@ typedef struct MapClient {
} MapClient;
QemuMutex map_client_list_lock;
static QLIST_HEAD(map_client_list, MapClient) map_client_list
static QLIST_HEAD(, MapClient) map_client_list
= QLIST_HEAD_INITIALIZER(map_client_list);
static void cpu_unregister_map_client_do(MapClient *client)

2
fsdev/qemu-fsdev.c
View File

@ -18,7 +18,7 @@
#include "qemu/error-report.h"
#include "qemu/option.h"
static QTAILQ_HEAD(FsDriverEntry_head, FsDriverListEntry) fsdriver_entries =
static QTAILQ_HEAD(, FsDriverListEntry) fsdriver_entries =
QTAILQ_HEAD_INITIALIZER(fsdriver_entries);
static FsDriverTable FsDrivers[] = {

12
hw/alpha/typhoon.c
View File

@ -664,8 +664,8 @@ static bool window_translate(TyphoonWindow *win, hwaddr addr,
pte_addr |= (addr & (wsm | 0xfe000)) >> 10;
return pte_translate(pte_addr, ret);
} else {
/* Direct-mapped translation. */
return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret);
/* Direct-mapped translation. */
return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret);
}
}
@ -700,7 +700,7 @@ static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu,
/* Check the fourth window for DAC disable. */
if ((pchip->win[3].wba & 0x80000000000ull) == 0
&& window_translate(&pchip->win[3], addr, &ret)) {
&& window_translate(&pchip->win[3], addr, &ret)) {
goto success;
}
} else {
@ -711,7 +711,7 @@ static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu,
if (pchip->ctl & 0x40) {
/* See 10.1.4.4; in particular <39:35> is ignored. */
make_iommu_tlbe(0, 0x007ffffffffull, &ret);
goto success;
goto success;
}
}
@ -723,8 +723,8 @@ static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu,
pte_addr = pchip->win[3].tba & 0x7ffc00000ull;
pte_addr |= (addr & 0xffffe000u) >> 10;
if (pte_translate(pte_addr, &ret)) {
goto success;
}
goto success;
}
}
}
}

2
hw/arm/stellaris.c
View File

@ -131,7 +131,7 @@ static void gptm_tick(void *opaque)
s->state |= 1;
if ((s->control & 0x20)) {
/* Output trigger. */
qemu_irq_pulse(s->trigger);
qemu_irq_pulse(s->trigger);
}
if (s->mode[0] & 1) {
/* One-shot. */

8
hw/block/nvme.h
View File

@ -29,8 +29,8 @@ typedef struct NvmeSQueue {
uint64_t dma_addr;
QEMUTimer *timer;
NvmeRequest *io_req;
QTAILQ_HEAD(sq_req_list, NvmeRequest) req_list;
QTAILQ_HEAD(out_req_list, NvmeRequest) out_req_list;
QTAILQ_HEAD(, NvmeRequest) req_list;
QTAILQ_HEAD(, NvmeRequest) out_req_list;
QTAILQ_ENTRY(NvmeSQueue) entry;
} NvmeSQueue;
@ -45,8 +45,8 @@ typedef struct NvmeCQueue {
uint32_t size;
uint64_t dma_addr;
QEMUTimer *timer;
QTAILQ_HEAD(sq_list, NvmeSQueue) sq_list;
QTAILQ_HEAD(cq_req_list, NvmeRequest) req_list;
QTAILQ_HEAD(, NvmeSQueue) sq_list;
QTAILQ_HEAD(, NvmeRequest) req_list;
} NvmeCQueue;
typedef struct NvmeNamespace {

6
hw/block/xen_disk.c
View File

@ -82,9 +82,9 @@ struct XenBlkDev {
int more_work;
/* request lists */
QLIST_HEAD(inflight_head, ioreq) inflight;
QLIST_HEAD(finished_head, ioreq) finished;
QLIST_HEAD(freelist_head, ioreq) freelist;
QLIST_HEAD(, ioreq) inflight;
QLIST_HEAD(, ioreq) finished;
QLIST_HEAD(, ioreq) freelist;
int requests_total;
int requests_inflight;
int requests_finished;

18
hw/char/sh_serial.c
View File

@ -90,7 +90,7 @@ static void sh_serial_write(void *opaque, hwaddr offs,
#ifdef DEBUG_SERIAL
printf("sh_serial: write offs=0x%02x val=0x%02x\n",
offs, val);
offs, val);
#endif
switch(offs) {
case 0x00: /* SMR */
@ -98,17 +98,17 @@ static void sh_serial_write(void *opaque, hwaddr offs,
return;
case 0x04: /* BRR */
s->brr = val;
return;
return;
case 0x08: /* SCR */
/* TODO : For SH7751, SCIF mask should be 0xfb. */
s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
if (!(val & (1 << 5)))
s->flags |= SH_SERIAL_FLAG_TEND;
if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
qemu_set_irq(s->txi, val & (1 << 7));
qemu_set_irq(s->txi, val & (1 << 7));
}
if (!(val & (1 << 6))) {
qemu_set_irq(s->rxi, 0);
qemu_set_irq(s->rxi, 0);
}
return;
case 0x0c: /* FTDR / TDR */
@ -117,9 +117,9 @@ static void sh_serial_write(void *opaque, hwaddr offs,
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
s->dr = val;
s->flags &= ~SH_SERIAL_FLAG_TDE;
}
s->dr = val;
s->flags &= ~SH_SERIAL_FLAG_TDE;
return;
#if 0
case 0x14: /* FRDR / RDR */
@ -210,7 +210,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
break;
case 0x04:
ret = s->brr;
break;
break;
case 0x08:
ret = s->scr;
break;
@ -288,7 +288,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
}
#ifdef DEBUG_SERIAL
printf("sh_serial: read offs=0x%02x val=0x%x\n",
offs, ret);
offs, ret);
#endif
if (ret & ~((1 << 16) - 1)) {

2
hw/char/virtio-serial-bus.c
View File

@ -696,7 +696,7 @@ static void virtio_serial_save_device(VirtIODevice *vdev, QEMUFile *f)
qemu_put_byte(f, port->guest_connected);
qemu_put_byte(f, port->host_connected);
elem_popped = 0;
elem_popped = 0;
if (port->elem) {
elem_popped = 1;
}

58
hw/char/xen_console.c
View File

@ -60,34 +60,34 @@ static void buffer_append(struct XenConsole *con)
size = prod - cons;
if ((size == 0) || (size > sizeof(intf->out)))
return;
return;
if ((buffer->capacity - buffer->size) < size) {
buffer->capacity += (size + 1024);
buffer->data = g_realloc(buffer->data, buffer->capacity);
buffer->capacity += (size + 1024);
buffer->data = g_realloc(buffer->data, buffer->capacity);
}
while (cons != prod)
buffer->data[buffer->size++] = intf->out[
MASK_XENCONS_IDX(cons++, intf->out)];
buffer->data[buffer->size++] = intf->out[
MASK_XENCONS_IDX(cons++, intf->out)];
xen_mb();
intf->out_cons = cons;
xen_pv_send_notify(&con->xendev);
if (buffer->max_capacity &&
buffer->size > buffer->max_capacity) {
/* Discard the middle of the data. */
buffer->size > buffer->max_capacity) {
/* Discard the middle of the data. */
size_t over = buffer->size - buffer->max_capacity;
uint8_t *maxpos = buffer->data + buffer->max_capacity;
size_t over = buffer->size - buffer->max_capacity;
uint8_t *maxpos = buffer->data + buffer->max_capacity;
memmove(maxpos - over, maxpos, over);
buffer->data = g_realloc(buffer->data, buffer->max_capacity);
buffer->size = buffer->capacity = buffer->max_capacity;
memmove(maxpos - over, maxpos, over);
buffer->data = g_realloc(buffer->data, buffer->max_capacity);
buffer->size = buffer->capacity = buffer->max_capacity;
if (buffer->consumed > buffer->max_capacity - over)
buffer->consumed = buffer->max_capacity - over;
if (buffer->consumed > buffer->max_capacity - over)
buffer->consumed = buffer->max_capacity - over;
}
}
@ -95,8 +95,8 @@ static void buffer_advance(struct buffer *buffer, size_t len)
{
buffer->consumed += len;
if (buffer->consumed == buffer->size) {
buffer->consumed = 0;
buffer->size = 0;
buffer->consumed = 0;
buffer->size = 0;
}
}
@ -111,7 +111,7 @@ static int ring_free_bytes(struct XenConsole *con)
space = prod - cons;
if (space > sizeof(intf->in))
return 0; /* ring is screwed: ignore it */
return 0; /* ring is screwed: ignore it */
return (sizeof(intf->in) - space);
}
@ -132,12 +132,12 @@ static void xencons_receive(void *opaque, const uint8_t *buf, int len)
max = ring_free_bytes(con);
/* The can_receive() func limits this, but check again anyway */
if (max < len)
len = max;
len = max;
prod = intf->in_prod;
for (i = 0; i < len; i++) {
intf->in[MASK_XENCONS_IDX(prod++, intf->in)] =
buf[i];
intf->in[MASK_XENCONS_IDX(prod++, intf->in)] =
buf[i];
}
xen_wmb();
intf->in_prod = prod;
@ -228,11 +228,11 @@ static int con_initialise(struct XenDevice *xendev)
int limit;
if (xenstore_read_int(con->console, "ring-ref", &con->ring_ref) == -1)
return -1;
return -1;
if (xenstore_read_int(con->console, "port", &con->xendev.remote_port) == -1)
return -1;
return -1;
if (xenstore_read_int(con->console, "limit", &limit) == 0)
con->buffer.max_capacity = limit;
con->buffer.max_capacity = limit;
if (!xendev->dev) {
xen_pfn_t mfn = con->ring_ref;
@ -244,7 +244,7 @@ static int con_initialise(struct XenDevice *xendev)
PROT_READ | PROT_WRITE);
}
if (!con->sring)
return -1;
return -1;
xen_be_bind_evtchn(&con->xendev);
qemu_chr_fe_set_handlers(&con->chr, xencons_can_receive,
@ -252,10 +252,10 @@ static int con_initialise(struct XenDevice *xendev)
xen_pv_printf(xendev, 1,
"ring mfn %d, remote port %d, local port %d, limit %zd\n",
con->ring_ref,
con->xendev.remote_port,
con->xendev.local_port,
con->buffer.max_capacity);
con->ring_ref,
con->xendev.remote_port,
con->xendev.local_port,
con->buffer.max_capacity);
return 0;
}
@ -282,7 +282,7 @@ static void con_event(struct XenDevice *xendev)
buffer_append(con);
if (con->buffer.size - con->buffer.consumed)
xencons_send(con);
xencons_send(con);
}
/* -------------------------------------------------------------------- */

28
hw/core/loader.c
View File

@ -244,26 +244,26 @@ int load_aout(const char *filename, hwaddr addr, int max_sz,
case OMAGIC:
if (e.a_text + e.a_data > max_sz)
goto fail;
lseek(fd, N_TXTOFF(e), SEEK_SET);
size = read_targphys(filename, fd, addr, e.a_text + e.a_data);
if (size < 0)
goto fail;
break;
lseek(fd, N_TXTOFF(e), SEEK_SET);
size = read_targphys(filename, fd, addr, e.a_text + e.a_data);
if (size < 0)
goto fail;
break;
case NMAGIC:
if (N_DATADDR(e, target_page_size) + e.a_data > max_sz)
goto fail;
lseek(fd, N_TXTOFF(e), SEEK_SET);
size = read_targphys(filename, fd, addr, e.a_text);
if (size < 0)
goto fail;
lseek(fd, N_TXTOFF(e), SEEK_SET);
size = read_targphys(filename, fd, addr, e.a_text);
if (size < 0)
goto fail;
ret = read_targphys(filename, fd, addr + N_DATADDR(e, target_page_size),
e.a_data);
if (ret < 0)
goto fail;
size += ret;
break;
if (ret < 0)
goto fail;
size += ret;
break;
default:
goto fail;
goto fail;
}
close(fd);
return size;

4
hw/core/qdev.c
View File

@ -158,7 +158,7 @@ DeviceState *qdev_try_create(BusState *bus, const char *type)
return dev;
}
static QTAILQ_HEAD(device_listeners, DeviceListener) device_listeners
static QTAILQ_HEAD(, DeviceListener) device_listeners
= QTAILQ_HEAD_INITIALIZER(device_listeners);
enum ListenerDirection { Forward, Reverse };
@ -177,7 +177,7 @@ enum ListenerDirection { Forward, Reverse };
break; \
case Reverse: \
QTAILQ_FOREACH_REVERSE(_listener, &device_listeners, \
device_listeners, link) { \
link) { \
if (_listener->_callback) { \
_listener->_callback(_listener, ##_args); \
} \

2
hw/core/reset.c
View File

@ -35,7 +35,7 @@ typedef struct QEMUResetEntry {
void *opaque;
} QEMUResetEntry;
static QTAILQ_HEAD(reset_handlers, QEMUResetEntry) reset_handlers =
static QTAILQ_HEAD(, QEMUResetEntry) reset_handlers =
QTAILQ_HEAD_INITIALIZER(reset_handlers);
void qemu_register_reset(QEMUResetHandler *func, void *opaque)

6
hw/display/tc6393xb.c
View File

@ -319,7 +319,7 @@ static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
SCR_REG_B(DEBUG);
}
fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
(uint32_t) addr, value & 0xff);
(uint32_t) addr, value & 0xff);
}
#undef SCR_REG_B
#undef SCR_REG_W
@ -358,7 +358,7 @@ static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t val
return;
}
fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
(uint32_t) addr, value & 0xff);
(uint32_t) addr, value & 0xff);
}
static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
@ -421,7 +421,7 @@ static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
return;
}
fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
(uint32_t) addr, value & 0xff);
(uint32_t) addr, value & 0xff);
}
#define BITS 8

8
hw/display/vga.c
View File

@ -85,10 +85,10 @@ const uint8_t gr_mask[16] = {
#define cbswap_32(__x) \
((uint32_t)( \
(((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
(((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
#ifdef HOST_WORDS_BIGENDIAN
#define PAT(x) cbswap_32(x)

6
hw/display/virtio-gpu-3d.c
View File

@ -498,9 +498,9 @@ static void virgl_write_fence(void *opaque, uint32_t fence)
QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
/*
* the guest can end up emitting fences out of order
* so we should check all fenced cmds not just the first one.
*/
* the guest can end up emitting fences out of order
* so we should check all fenced cmds not just the first one.
*/
if (cmd->cmd_hdr.fence_id > fence) {
continue;
}

4
hw/dma/pxa2xx_dma.c
View File

@ -228,7 +228,7 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s)
!(ch->state & DCSR_NODESCFETCH))
pxa2xx_dma_descriptor_fetch(s, c);
break;
}
}
}
ch->cmd = (ch->cmd & ~DCMD_LEN) | length;
@ -283,7 +283,7 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
case DCSR0 ... DCSR31:
channel = offset >> 2;
if (s->chan[channel].request)
if (s->chan[channel].request)
return s->chan[channel].state | DCSR_REQPEND;
return s->chan[channel].state;

2
hw/dma/soc_dma.c
View File

@ -345,7 +345,7 @@ void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base,
while (entry < dma->memmap + dma->memmap_size &&
entry->addr <= virt_base)
entry ++;
}
}
memmove(entry + 1, entry,
(uint8_t *) (dma->memmap + dma->memmap_size ++) -

2
hw/gpio/max7310.c
View File

@ -118,7 +118,7 @@ static int max7310_tx(I2CSlave *i2c, uint8_t data)
break;
case 0x00: /* Input port - ignore writes */
break;
break;
default:
#ifdef VERBOSE
printf("%s: unknown register %02x\n", __func__, s->command);

4
hw/i386/xen/xen-hvm.c
View File

@ -570,7 +570,7 @@ static void xen_io_del(MemoryListener *listener,
}
static void xen_device_realize(DeviceListener *listener,
DeviceState *dev)
DeviceState *dev)
{
XenIOState *state = container_of(listener, XenIOState, device_listener);
@ -588,7 +588,7 @@ static void xen_device_realize(DeviceListener *listener,
}
static void xen_device_unrealize(DeviceListener *listener,
DeviceState *dev)
DeviceState *dev)
{
XenIOState *state = container_of(listener, XenIOState, device_listener);

2
hw/i386/xen/xen-mapcache.c
View File

@ -71,7 +71,7 @@ typedef struct MapCacheRev {
typedef struct MapCache {
MapCacheEntry *entry;
unsigned long nr_buckets;
QTAILQ_HEAD(map_cache_head, MapCacheRev) locked_entries;
QTAILQ_HEAD(, MapCacheRev) locked_entries;
/* For most cases (>99.9%), the page address is the same. */
MapCacheEntry *last_entry;

94
hw/ide/core.c
View File

@ -575,16 +575,16 @@ int64_t ide_get_sector(IDEState *s)
int64_t sector_num;
if (s->select & 0x40) {
/* lba */
if (!s->lba48) {
sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
(s->lcyl << 8) | s->sector;
} else {
sector_num = ((int64_t)s->hob_hcyl << 40) |
((int64_t) s->hob_lcyl << 32) |
((int64_t) s->hob_sector << 24) |
((int64_t) s->hcyl << 16) |
((int64_t) s->lcyl << 8) | s->sector;
}
if (!s->lba48) {
sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
(s->lcyl << 8) | s->sector;
} else {
sector_num = ((int64_t)s->hob_hcyl << 40) |
((int64_t) s->hob_lcyl << 32) |
((int64_t) s->hob_sector << 24) |
((int64_t) s->hcyl << 16) |
((int64_t) s->lcyl << 8) | s->sector;
}
} else {
sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
(s->select & 0x0f) * s->sectors + (s->sector - 1);
@ -596,19 +596,19 @@ void ide_set_sector(IDEState *s, int64_t sector_num)
{
unsigned int cyl, r;
if (s->select & 0x40) {
if (!s->lba48) {
if (!s->lba48) {
s->select = (s->select & 0xf0) | (sector_num >> 24);
s->hcyl = (sector_num >> 16);
s->lcyl = (sector_num >> 8);
s->sector = (sector_num);
} else {
s->sector = sector_num;
s->lcyl = sector_num >> 8;
s->hcyl = sector_num >> 16;
s->hob_sector = sector_num >> 24;
s->hob_lcyl = sector_num >> 32;
s->hob_hcyl = sector_num >> 40;
}
} else {
s->sector = sector_num;
s->lcyl = sector_num >> 8;
s->hcyl = sector_num >> 16;
s->hob_sector = sector_num >> 24;
s->hob_lcyl = sector_num >> 32;
s->hob_hcyl = sector_num >> 40;
}
} else {
cyl = sector_num / (s->heads * s->sectors);
r = sector_num % (s->heads * s->sectors);
@ -1188,17 +1188,17 @@ static void ide_cmd_lba48_transform(IDEState *s, int lba48)
* full sector count in ->nsector and ignore ->hob_nsector from now
*/
if (!s->lba48) {
if (!s->nsector)
s->nsector = 256;
if (!s->nsector)
s->nsector = 256;
} else {
if (!s->nsector && !s->hob_nsector)
s->nsector = 65536;
else {
int lo = s->nsector;
int hi = s->hob_nsector;
if (!s->nsector && !s->hob_nsector)
s->nsector = 65536;
else {
int lo = s->nsector;
int hi = s->hob_nsector;
s->nsector = (hi << 8) | lo;
}
s->nsector = (hi << 8) | lo;
}
}
}
@ -1258,35 +1258,35 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
bus->ifs[1].feature = val;
break;
case ATA_IOPORT_WR_SECTOR_COUNT:
ide_clear_hob(bus);
bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
ide_clear_hob(bus);
bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
bus->ifs[0].nsector = val;
bus->ifs[1].nsector = val;
break;
case ATA_IOPORT_WR_SECTOR_NUMBER:
ide_clear_hob(bus);
bus->ifs[0].hob_sector = bus->ifs[0].sector;
bus->ifs[1].hob_sector = bus->ifs[1].sector;
ide_clear_hob(bus);
bus->ifs[0].hob_sector = bus->ifs[0].sector;
bus->ifs[1].hob_sector = bus->ifs[1].sector;
bus->ifs[0].sector = val;
bus->ifs[1].sector = val;
break;
case ATA_IOPORT_WR_CYLINDER_LOW:
ide_clear_hob(bus);
bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
ide_clear_hob(bus);
bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
bus->ifs[0].lcyl = val;
bus->ifs[1].lcyl = val;
break;
case ATA_IOPORT_WR_CYLINDER_HIGH:
ide_clear_hob(bus);
bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
ide_clear_hob(bus);
bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
bus->ifs[0].hcyl = val;
bus->ifs[1].hcyl = val;
break;
case ATA_IOPORT_WR_DEVICE_HEAD:
/* FIXME: HOB readback uses bit 7 */
/* FIXME: HOB readback uses bit 7 */
bus->ifs[0].select = (val & ~0x10) | 0xa0;
bus->ifs[1].select = (val | 0x10) | 0xa0;
/* select drive */
@ -2146,7 +2146,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
} else if (!hob) {
ret = s->error;
} else {
ret = s->hob_feature;
ret = s->hob_feature;
}
break;
case ATA_IOPORT_RR_SECTOR_COUNT:
@ -2155,7 +2155,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
} else if (!hob) {
ret = s->nsector & 0xff;
} else {
ret = s->hob_nsector;
ret = s->hob_nsector;
}
break;
case ATA_IOPORT_RR_SECTOR_NUMBER:
@ -2164,7 +2164,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
} else if (!hob) {
ret = s->sector;
} else {
ret = s->hob_sector;
ret = s->hob_sector;
}
break;
case ATA_IOPORT_RR_CYLINDER_LOW:
@ -2173,7 +2173,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
} else if (!hob) {
ret = s->lcyl;
} else {
ret = s->hob_lcyl;
ret = s->hob_lcyl;
}
break;
case ATA_IOPORT_RR_CYLINDER_HIGH:
@ -2182,7 +2182,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
} else if (!hob) {
ret = s->hcyl;
} else {
ret = s->hob_hcyl;
ret = s->hob_hcyl;
}
break;
case ATA_IOPORT_RR_DEVICE_HEAD:
@ -2847,7 +2847,7 @@ static const VMStateDescription vmstate_ide_drive_pio_state = {
.fields = (VMStateField[]) {
VMSTATE_INT32(req_nb_sectors, IDEState),
VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
vmstate_info_uint8, uint8_t),
vmstate_info_uint8, uint8_t),
VMSTATE_INT32(cur_io_buffer_offset, IDEState),
VMSTATE_INT32(cur_io_buffer_len, IDEState),
VMSTATE_UINT8(end_transfer_fn_idx, IDEState),

2
hw/input/lm832x.c
View File

@ -66,7 +66,7 @@ typedef struct {
struct {
uint16_t file[256];
uint8_t faddr;
uint8_t faddr;
uint8_t addr[3];
QEMUTimer *tm[3];
} pwm;

2
hw/input/pckbd.c
View File

@ -55,7 +55,7 @@
#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
#define KBD_CCMD_WRITE_OBUF 0xD2
#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
initiated by the auxiliary device */
initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */

2
hw/input/tsc210x.c
View File

@ -577,7 +577,7 @@ static void tsc2102_control_register_write(
case 0x01: /* Status / Keypad Control */
if ((s->model & 0xff00) == 0x2100)
s->pin_func = value >> 14;
else {
else {
s->kb.scan = (value >> 14) & 1;
s->kb.debounce = (value >> 11) & 7;
if (s->kb.intr && s->kb.scan) {

2
hw/intc/apic.c
View File

@ -442,7 +442,7 @@ static int apic_find_dest(uint8_t dest)
for (i = 0; i < MAX_APICS; i++) {
apic = local_apics[i];
if (apic && apic->id == dest)
if (apic && apic->id == dest)
return i;
if (!apic)
break;

6
hw/mips/gt64xxx_pci.c
View File

@ -395,7 +395,7 @@ static void gt64120_writel (void *opaque, hwaddr addr,
s->regs[GT_CPU] = val;
break;
case GT_MULTI:
/* Read-only register as only one GT64xxx is present on the CPU bus */
/* Read-only register as only one GT64xxx is present on the CPU bus */
break;
/* CPU Address Decode */
@ -457,13 +457,13 @@ static void gt64120_writel (void *opaque, hwaddr addr,
case GT_CPUERR_DATALO:
case GT_CPUERR_DATAHI:
case GT_CPUERR_PARITY:
/* Read-only registers, do nothing */
/* Read-only registers, do nothing */
break;
/* CPU Sync Barrier */
case GT_PCI0SYNC:
case GT_PCI1SYNC:
/* Read-only registers, do nothing */
/* Read-only registers, do nothing */
break;
/* SDRAM and Device Address Decode */

4
hw/mips/mips_r4k.c
View File

@ -239,7 +239,7 @@ void mips_r4k_init(MachineState *machine)
sector_len, mips_rom / sector_len,
4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
}
}
} else if (!qtest_enabled()) {
/* not fatal */
warn_report("could not load MIPS bios '%s'", bios_name);
@ -285,7 +285,7 @@ void mips_r4k_init(MachineState *machine)
for(i = 0; i < MAX_IDE_BUS; i++)
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
hd[MAX_IDE_DEVS * i],
hd[MAX_IDE_DEVS * i + 1]);
hd[MAX_IDE_DEVS * i + 1]);
isa_create_simple(isa_bus, TYPE_I8042);
}

6
hw/misc/max111x.c
View File

@ -43,9 +43,9 @@ typedef struct {
#define CB_START (1 << 7)
#define CHANNEL_NUM(v, b0, b1, b2) \
((((v) >> (2 + (b0))) & 4) | \
(((v) >> (3 + (b1))) & 2) | \
(((v) >> (4 + (b2))) & 1))
((((v) >> (2 + (b0))) & 4) | \
(((v) >> (3 + (b1))) & 2) | \
(((v) >> (4 + (b2))) & 1))
static uint32_t max111x_read(MAX111xState *s)
{

4
hw/misc/omap_l4.c
View File

@ -112,8 +112,8 @@ static const MemoryRegionOps omap_l4ta_ops = {
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
const struct omap_l4_region_s *regions,
const struct omap_l4_agent_info_s *agents,
int cs)
const struct omap_l4_agent_info_s *agents,
int cs)
{
int i;
struct omap_target_agent_s *ta = NULL;

16
hw/net/mipsnet.c
View File

@ -112,27 +112,27 @@ static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
addr &= 0x3f;
switch (addr) {
case MIPSNET_DEV_ID:
ret = be32_to_cpu(0x4d495053); /* MIPS */
ret = be32_to_cpu(0x4d495053); /* MIPS */
break;
case MIPSNET_DEV_ID + 4:
ret = be32_to_cpu(0x4e455430); /* NET0 */
ret = be32_to_cpu(0x4e455430); /* NET0 */
break;
case MIPSNET_BUSY:
ret = s->busy;
ret = s->busy;
break;
case MIPSNET_RX_DATA_COUNT:
ret = s->rx_count;
ret = s->rx_count;
break;
case MIPSNET_TX_DATA_COUNT:
ret = s->tx_count;
ret = s->tx_count;
break;
case MIPSNET_INT_CTL:
ret = s->intctl;
ret = s->intctl;
s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
break;
case MIPSNET_INTERRUPT_INFO:
/* XXX: This seems to be a per-VPE interrupt number. */
ret = 0;
ret = 0;
break;
case MIPSNET_RX_DATA_BUFFER:
if (s->rx_count) {
@ -161,7 +161,7 @@ static void mipsnet_ioport_write(void *opaque, hwaddr addr,
trace_mipsnet_write(addr, val);
switch (addr) {
case MIPSNET_TX_DATA_COUNT:
s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
s->tx_written = 0;
break;
case MIPSNET_INT_CTL:

44
hw/net/ne2000.c
View File

@ -145,7 +145,7 @@ static void ne2000_update_irq(NE2000State *s)
isr = (s->isr & s->imr) & 0x7f;
#if defined(DEBUG_NE2000)
printf("NE2000: Set IRQ to %d (%02x %02x)\n",
isr ? 1 : 0, s->isr, s->imr);
isr ? 1 : 0, s->isr, s->imr);
#endif
qemu_set_irq(s->irq, (isr != 0));
}
@ -396,12 +396,12 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
case EN0_ISR:
ret = s->isr;
break;
case EN0_RSARLO:
ret = s->rsar & 0x00ff;
break;
case EN0_RSARHI:
ret = s->rsar >> 8;
break;
case EN0_RSARLO:
ret = s->rsar & 0x00ff;
break;
case EN0_RSARHI:
ret = s->rsar >> 8;
break;
case EN1_PHYS ... EN1_PHYS + 5:
ret = s->phys[offset - EN1_PHYS];
break;
@ -420,21 +420,21 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
case EN2_STOPPG:
ret = s->stop >> 8;
break;
case EN0_RTL8029ID0:
ret = 0x50;
break;
case EN0_RTL8029ID1:
ret = 0x43;
break;
case EN3_CONFIG0:
ret = 0; /* 10baseT media */
break;
case EN3_CONFIG2:
ret = 0x40; /* 10baseT active */
break;
case EN3_CONFIG3:
ret = 0x40; /* Full duplex */
break;
case EN0_RTL8029ID0:
ret = 0x50;
break;
case EN0_RTL8029ID1:
ret = 0x43;
break;
case EN3_CONFIG0:
ret = 0; /* 10baseT media */
break;
case EN3_CONFIG2:
ret = 0x40; /* 10baseT active */
break;
case EN3_CONFIG3:
ret = 0x40; /* Full duplex */
break;
default:
ret = 0x00;
break;

2
hw/net/rocker/rocker.c
View File

@ -1279,7 +1279,7 @@ static World *rocker_world_type_by_name(Rocker *r, const char *name)
for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) {
if (strcmp(name, world_name(r->worlds[i])) == 0) {
return r->worlds[i];
}
}
}
return NULL;
}

4
hw/net/virtio-net.c
View File

@ -1375,10 +1375,10 @@ static int32_t virtio_net_flush_tx(VirtIONetQueue *q)
n->guest_hdr_len, -1);
if (out_num == VIRTQUEUE_MAX_SIZE) {
goto drop;
}
}
out_num += 1;
out_sg = sg2;
}
}
}
/*
* If host wants to see the guest header as is, we can

6
hw/net/vmxnet3.c
View File

@ -137,7 +137,7 @@ typedef struct VMXNET3Class {
OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
static inline void vmxnet3_ring_init(PCIDevice *d,
Vmxnet3Ring *ring,
Vmxnet3Ring *ring,
hwaddr pa,
uint32_t size,
uint32_t cell_size,
@ -181,13 +181,13 @@ static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
}
static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
void *buff)
void *buff)
{
vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
}
static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
void *buff)
void *buff)
{
vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
}

2
hw/pci-host/pam.c
View File

@ -52,11 +52,13 @@ void init_pam(DeviceState *dev, MemoryRegion *ram_memory,
memory_region_init_alias(&mem->alias[2], OBJECT(dev), "pam-pci", ram_memory,
start, size);
memory_region_transaction_begin();
for (i = 0; i < 4; ++i) {
memory_region_set_enabled(&mem->alias[i], false);
memory_region_add_subregion_overlap(system_memory, start,
&mem->alias[i], 1);
}
memory_region_transaction_commit();
mem->current = 0;
}

2
hw/pci/msix.c
View File

@ -501,7 +501,7 @@ void msix_reset(PCIDevice *dev)
}
msix_clear_all_vectors(dev);
dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
msix_mask_all(dev, dev->msix_entries_nr);

44
hw/pci/pci.c
View File

@ -211,13 +211,13 @@ int pci_bar(PCIDevice *d, int reg)
static inline int pci_irq_state(PCIDevice *d, int irq_num)
{
return (d->irq_state >> irq_num) & 0x1;
return (d->irq_state >> irq_num) & 0x1;
}
static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
{
d->irq_state &= ~(0x1 << irq_num);
d->irq_state |= level << irq_num;
d->irq_state &= ~(0x1 << irq_num);
d->irq_state |= level << irq_num;
}
static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
@ -604,8 +604,8 @@ const VMStateDescription vmstate_pci_device = {
0, vmstate_info_pci_config,
PCIE_CONFIG_SPACE_SIZE),
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
vmstate_info_pci_irq_state,
PCI_NUM_PINS * sizeof(int32_t)),
vmstate_info_pci_irq_state,
PCI_NUM_PINS * sizeof(int32_t)),
VMSTATE_END_OF_LIST()
}
};
@ -657,21 +657,21 @@ static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
p = addr;
val = strtoul(p, &e, 16);
if (e == p)
return -1;
return -1;
if (*e == ':') {
bus = val;
p = e + 1;
val = strtoul(p, &e, 16);
if (e == p)
return -1;
if (*e == ':') {
dom = bus;
bus = val;
p = e + 1;
val = strtoul(p, &e, 16);
if (e == p)
return -1;
}
bus = val;
p = e + 1;
val = strtoul(p, &e, 16);
if (e == p)
return -1;
if (*e == ':') {
dom = bus;
bus = val;
p = e + 1;
val = strtoul(p, &e, 16);
if (e == p)
return -1;
}
}
slot = val;
@ -690,10 +690,10 @@ static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
/* if funcp == NULL func is 0 */
if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
return -1;
return -1;
if (*e)
return -1;
return -1;
*domp = dom;
*busp = bus;
@ -1250,7 +1250,7 @@ pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
}
static pcibus_t pci_bar_address(PCIDevice *d,
int reg, uint8_t type, pcibus_t size)
int reg, uint8_t type, pcibus_t size)
{
pcibus_t new_addr, last_addr;
int bar = pci_bar(d, reg);

2
hw/pci/pci_bridge.c
View File

@ -369,7 +369,7 @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
* let users address the bus using the device name.
*/
if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
br->bus_name = dev->qdev.id;
br->bus_name = dev->qdev.id;
}
qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),

2
hw/ppc/ppc405_uc.c
View File

@ -1885,7 +1885,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
*picp = pic;
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
/* XXX 405EP has no ECC interrupt */
ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
ram_bases, ram_sizes, do_init);
/* External bus controller */

4
hw/ppc/prep.c
View File

@ -538,7 +538,7 @@ static void ppc_prep_init(MachineState *machine)
nb_nics1 = NE2000_NB_MAX;
for(i = 0; i < nb_nics1; i++) {
if (nd_table[i].model == NULL) {
nd_table[i].model = g_strdup("ne2k_isa");
nd_table[i].model = g_strdup("ne2k_isa");
}
if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
@ -552,7 +552,7 @@ static void ppc_prep_init(MachineState *machine)
for(i = 0; i < MAX_IDE_BUS; i++) {
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
hd[2 * i],
hd[2 * i + 1]);
hd[2 * i + 1]);
}
cpu = POWERPC_CPU(first_cpu);

2
hw/ppc/spapr_iommu.c
View File

@ -42,7 +42,7 @@ enum sPAPRTCEAccess {
#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
static QLIST_HEAD(, sPAPRTCETable) spapr_tce_tables;
sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
{

10
hw/scsi/esp-pci.c
View File

@ -59,7 +59,7 @@
#define DMA_STAT_SCSIINT 0x10
#define DMA_STAT_BCMBLT 0x20
#define SBAC_STATUS 0x1000
#define SBAC_STATUS (1 << 24)
typedef struct PCIESPState {
/*< private >*/
@ -136,7 +136,7 @@ static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
pci->dma_regs[saddr] = val;
break;
case DMA_STAT:
if (!(pci->sbac & SBAC_STATUS)) {
if (pci->sbac & SBAC_STATUS) {
/* clear some bits on write */
uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
pci->dma_regs[DMA_STAT] &= ~(val & mask);
@ -157,7 +157,7 @@ static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
val |= DMA_STAT_SCSIINT;
}
if (pci->sbac & SBAC_STATUS) {
if (!(pci->sbac & SBAC_STATUS)) {
pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
DMA_STAT_DONE);
}
@ -313,8 +313,8 @@ static void esp_pci_hard_reset(DeviceState *dev)
static const VMStateDescription vmstate_esp_pci_scsi = {
.name = "pciespscsi",
.version_id = 0,
.minimum_version_id = 0,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),

33
hw/scsi/esp.c
View File

@ -286,11 +286,8 @@ static void esp_do_dma(ESPState *s)
esp_dma_done(s);
}
void esp_command_complete(SCSIRequest *req, uint32_t status,
size_t resid)
static void esp_report_command_complete(ESPState *s, uint32_t status)
{
ESPState *s = req->hba_private;
trace_esp_command_complete();
if (s->ti_size != 0) {
trace_esp_command_complete_unexpected();
@ -311,6 +308,23 @@ void esp_command_complete(SCSIRequest *req, uint32_t status,
}
}
void esp_command_complete(SCSIRequest *req, uint32_t status,
size_t resid)
{
ESPState *s = req->hba_private;
if (s->rregs[ESP_RSTAT] & STAT_INT) {
/* Defer handling command complete until the previous
* interrupt has been handled.
*/
trace_esp_command_complete_deferred();
s->deferred_status = status;
s->deferred_complete = true;
return;
}
esp_report_command_complete(s, status);
}
void esp_transfer_data(SCSIRequest *req, uint32_t len)
{
ESPState *s = req->hba_private;
@ -422,7 +436,10 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
s->rregs[ESP_RSTAT] &= ~STAT_TC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_lower_irq(s);
if (s->deferred_complete) {
esp_report_command_complete(s, s->deferred_status);
s->deferred_complete = false;
}
return old_val;
case ESP_TCHI:
/* Return the unique id if the value has never been written */
@ -582,6 +599,8 @@ const VMStateDescription vmstate_esp = {
VMSTATE_UINT32(ti_wptr, ESPState),
VMSTATE_BUFFER(ti_buf, ESPState),
VMSTATE_UINT32(status, ESPState),
VMSTATE_UINT32(deferred_status, ESPState),
VMSTATE_BOOL(deferred_complete, ESPState),
VMSTATE_UINT32(dma, ESPState),
VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16),
VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4),
@ -671,8 +690,8 @@ static void sysbus_esp_hard_reset(DeviceState *dev)
static const VMStateDescription vmstate_sysbus_esp_scsi = {
.name = "sysbusespscsi",
.version_id = 0,
.minimum_version_id = 0,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
VMSTATE_END_OF_LIST()

6
hw/scsi/lsi53c895a.c
View File

@ -1850,7 +1850,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
break;
case 0x0a: case 0x0b:
/* Openserver writes to these readonly registers on startup */
return;
return;
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
/* Linux writes to these readonly registers on startup. */
return;
@ -1884,8 +1884,8 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
/* nothing to do */
break;
case 0x1a: /* CTEST2 */
s->ctest2 = val & LSI_CTEST2_PCICIE;
break;
s->ctest2 = val & LSI_CTEST2_PCICIE;
break;
case 0x1b: /* CTEST3 */
s->ctest3 = val & 0x0f;
break;

2
hw/scsi/scsi-bus.c
View File

@ -1554,7 +1554,7 @@ SCSIDevice *scsi_device_find(SCSIBus *bus, int channel, int id, int lun)
BusChild *kid;
SCSIDevice *target_dev = NULL;
QTAILQ_FOREACH_REVERSE(kid, &bus->qbus.children, ChildrenHead, sibling) {
QTAILQ_FOREACH_REVERSE(kid, &bus->qbus.children, sibling) {
DeviceState *qdev = kid->child;
SCSIDevice *dev = SCSI_DEVICE(qdev);

1
hw/scsi/trace-events
View File

@ -167,6 +167,7 @@ esp_handle_satn_stop(uint32_t cmdlen) "cmdlen %d"
esp_write_response(uint32_t status) "Transfer status (status=%d)"
esp_do_dma(uint32_t cmdlen, uint32_t len) "command len %d + %d"
esp_command_complete(void) "SCSI Command complete"
esp_command_complete_deferred(void) "SCSI Command complete deferred"
esp_command_complete_unexpected(void) "SCSI command completed unexpectedly"
esp_command_complete_fail(void) "Command failed"
esp_transfer_data(uint32_t dma_left, int32_t ti_size) "transfer %d/%d"

16
hw/sh4/r2d.c
View File

@ -139,11 +139,11 @@ static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size)
case PA_IRLMSK:
return s->irlmsk;
case PA_OUTPORT:
return s->outport;
return s->outport;
case PA_POWOFF:
return 0x00;
return 0x00;
case PA_VERREG:
return 0x10;
return 0x10;
}
return 0;
@ -158,18 +158,18 @@ r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size)
case PA_IRLMSK:
s->irlmsk = value;
update_irl(s);
break;
break;
case PA_OUTPORT:
s->outport = value;
break;
s->outport = value;
break;
case PA_POWOFF:
if (value & 1) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
break;
case PA_VERREG:
/* Discard writes */
break;
/* Discard writes */
break;
}
}

4
hw/usb/ccid-card-emulated.c
View File

@ -119,11 +119,11 @@ struct EmulatedState {
char *db;
uint8_t atr[MAX_ATR_SIZE];
uint8_t atr_length;
QSIMPLEQ_HEAD(event_list, EmulEvent) event_list;
QSIMPLEQ_HEAD(, EmulEvent) event_list;
QemuMutex event_list_mutex;
QemuThread event_thread_id;
VReader *reader;
QSIMPLEQ_HEAD(guest_apdu_list, EmulEvent) guest_apdu_list;
QSIMPLEQ_HEAD(, EmulEvent) guest_apdu_list;
QemuMutex vreader_mutex; /* and guest_apdu_list mutex */
QemuMutex handle_apdu_mutex;
QemuCond handle_apdu_cond;

2
hw/usb/combined-packet.c
View File

@ -64,7 +64,7 @@ void usb_combined_input_packet_complete(USBDevice *dev, USBPacket *p)
status = combined->first->status;
actual_length = combined->first->actual_length;
short_not_ok = QTAILQ_LAST(&combined->packets, packets_head)->short_not_ok;
short_not_ok = QTAILQ_LAST(&combined->packets)->short_not_ok;
QTAILQ_FOREACH_SAFE(p, &combined->packets, combined_entry, next) {
if (!done) {

2
hw/usb/dev-bluetooth.c
View File

@ -46,7 +46,7 @@ struct USBBtState {
struct usb_hci_out_fifo_s {
uint8_t data[4096];
int len;
int len;
} outcmd, outacl, outsco;
};

6
hw/usb/dev-hid.c
View File

@ -592,12 +592,12 @@ static void usb_hid_handle_control(USBDevice *dev, USBPacket *p,
switch (value >> 8) {
case 0x22:
if (hs->kind == HID_MOUSE) {
memcpy(data, qemu_mouse_hid_report_descriptor,
sizeof(qemu_mouse_hid_report_descriptor));
memcpy(data, qemu_mouse_hid_report_descriptor,
sizeof(qemu_mouse_hid_report_descriptor));
p->actual_length = sizeof(qemu_mouse_hid_report_descriptor);
} else if (hs->kind == HID_TABLET) {
memcpy(data, qemu_tablet_hid_report_descriptor,
sizeof(qemu_tablet_hid_report_descriptor));
sizeof(qemu_tablet_hid_report_descriptor));
p->actual_length = sizeof(qemu_tablet_hid_report_descriptor);
} else if (hs->kind == HID_KEYBOARD) {
memcpy(data, qemu_keyboard_hid_report_descriptor,

14
hw/usb/dev-hub.c
View File

@ -147,13 +147,13 @@ static const USBDesc desc_hub = {
static const uint8_t qemu_hub_hub_descriptor[] =
{
0x00, /* u8 bLength; patched in later */
0x29, /* u8 bDescriptorType; Hub-descriptor */
0x00, /* u8 bNbrPorts; (patched later) */
0x0a, /* u16 wHubCharacteristics; */
0x00, /* (per-port OC, no power switching) */
0x01, /* u8 bPwrOn2pwrGood; 2ms */
0x00 /* u8 bHubContrCurrent; 0 mA */
0x00, /* u8 bLength; patched in later */
0x29, /* u8 bDescriptorType; Hub-descriptor */
0x00, /* u8 bNbrPorts; (patched later) */
0x0a, /* u16 wHubCharacteristics; */
0x00, /* (per-port OC, no power switching) */
0x01, /* u8 bPwrOn2pwrGood; 2ms */
0x00 /* u8 bHubContrCurrent; 0 mA */
/* DeviceRemovable and PortPwrCtrlMask patched in later */
};

4
hw/usb/dev-mtp.c
View File

@ -191,7 +191,7 @@ struct MTPState {
#ifdef CONFIG_INOTIFY1
/* inotify descriptor */
int inotifyfd;
QTAILQ_HEAD(events, MTPMonEntry) events;
QTAILQ_HEAD(, MTPMonEntry) events;
#endif
/* Responder is expecting a write operation */
bool write_pending;
@ -1989,7 +1989,7 @@ static void usb_mtp_handle_data(USBDevice *dev, USBPacket *p)
case EP_EVENT:
#ifdef CONFIG_INOTIFY1
if (!QTAILQ_EMPTY(&s->events)) {
struct MTPMonEntry *e = QTAILQ_LAST(&s->events, events);
struct MTPMonEntry *e = QTAILQ_LAST(&s->events);
uint32_t handle;
int len = sizeof(container) + sizeof(uint32_t);

2
hw/usb/dev-network.c
View File

@ -648,7 +648,7 @@ typedef struct USBNetState {
char usbstring_mac[13];
NICState *nic;
NICConf conf;
QTAILQ_HEAD(rndis_resp_head, rndis_response) rndis_resp;
QTAILQ_HEAD(, rndis_response) rndis_resp;
} USBNetState;
#define TYPE_USB_NET "usb-net"

2
hw/usb/hcd-ehci.c
View File

@ -1823,7 +1823,7 @@ static int ehci_state_fetchqtd(EHCIQueue *q)
break;
case EHCI_ASYNC_INFLIGHT:
/* Check if the guest has added new tds to the queue */
again = ehci_fill_queue(QTAILQ_LAST(&q->packets, pkts_head));
again = ehci_fill_queue(QTAILQ_LAST(&q->packets));
/* Unfinished async handled packet, go horizontal */
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
break;

2
hw/usb/hcd-ehci.h
View File

@ -247,7 +247,7 @@ struct EHCIQueue {
uint32_t qtdaddr; /* address QTD read from */
int last_pid; /* pid of last packet executed */
USBDevice *dev;
QTAILQ_HEAD(pkts_head, EHCIPacket) packets;
QTAILQ_HEAD(, EHCIPacket) packets;
};
typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;

8
hw/usb/hcd-uhci.c
View File

@ -99,7 +99,7 @@ struct UHCIQueue {
UHCIState *uhci;
USBEndpoint *ep;
QTAILQ_ENTRY(UHCIQueue) next;
QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs;
QTAILQ_HEAD(, UHCIAsync) asyncs;
int8_t valid;
};
@ -837,7 +837,7 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
}
if (!async->done) {
UHCI_TD last_td;
UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head);
UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs);
/*
* While we are waiting for the current td to complete, the guest
* may have added more tds to the queue. Note we re-read the td
@ -1056,8 +1056,8 @@ static void uhci_process_frame(UHCIState *s)
link = qh.link;
} else {
/* QH with elements */
curr_qh = link;
link = qh.el_link;
curr_qh = link;
link = qh.el_link;
}
continue;
}

6
hw/usb/xen-usb.c
View File

@ -72,7 +72,7 @@ struct usbback_stub {
USBPort port;
unsigned int speed;
bool attached;
QTAILQ_HEAD(submit_q_head, usbback_req) submit_q;
QTAILQ_HEAD(, usbback_req) submit_q;
};
struct usbback_req {
@ -108,8 +108,8 @@ struct usbback_info {
int num_ports;
int usb_ver;
bool ring_error;
QTAILQ_HEAD(req_free_q_head, usbback_req) req_free_q;
QSIMPLEQ_HEAD(hotplug_q_head, usbback_hotplug) hotplug_q;
QTAILQ_HEAD(, usbback_req) req_free_q;
QSIMPLEQ_HEAD(, usbback_hotplug) hotplug_q;
struct usbback_stub ports[USBBACK_MAXPORTS];
struct usbback_stub *addr_table[USB_DEV_ADDR_SIZE];
QEMUBH *bh;

4
hw/vfio/common.c
View File

@ -37,9 +37,9 @@
#include "trace.h"
#include "qapi/error.h"
struct vfio_group_head vfio_group_list =
VFIOGroupList vfio_group_list =
QLIST_HEAD_INITIALIZER(vfio_group_list);
struct vfio_as_head vfio_address_spaces =
static QLIST_HEAD(, VFIOAddressSpace) vfio_address_spaces =
QLIST_HEAD_INITIALIZER(vfio_address_spaces);
#ifdef CONFIG_KVM

2
hw/watchdog/watchdog.c
View File

@ -32,7 +32,7 @@
#include "qemu/help_option.h"
static WatchdogAction watchdog_action = WATCHDOG_ACTION_RESET;
static QLIST_HEAD(watchdog_list, WatchdogTimerModel) watchdog_list;
static QLIST_HEAD(, WatchdogTimerModel) watchdog_list;
void watchdog_add_model(WatchdogTimerModel *model)
{

1
hw/watchdog/wdt_i6300esb.c
View File

@ -449,7 +449,6 @@ static void i6300esb_realize(PCIDevice *dev, Error **errp)
memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
"i6300esb", 0x10);
pci_register_bar(&d->dev, 0, 0, &d->io_mem);
/* qemu_register_coalesced_mmio (addr, 0x10); ? */
}
static void i6300esb_exit(PCIDevice *dev)

2
hw/xen/xen_devconfig.c
View File

@ -6,7 +6,7 @@
/* ------------------------------------------------------------- */
static int xen_config_dev_dirs(const char *ftype, const char *btype, int vdev,
char *fe, char *be, int len)
char *fe, char *be, int len)
{
char *dom;

4
hw/xen/xen_pvdev.c
View File

@ -31,10 +31,10 @@ struct xs_dirs {
QTAILQ_ENTRY(xs_dirs) list;
};
static QTAILQ_HEAD(xs_dirs_head, xs_dirs) xs_cleanup =
static QTAILQ_HEAD(, xs_dirs) xs_cleanup =
QTAILQ_HEAD_INITIALIZER(xs_cleanup);
static QTAILQ_HEAD(XenDeviceHead, XenDevice) xendevs =
static QTAILQ_HEAD(, XenDevice) xendevs =
QTAILQ_HEAD_INITIALIZER(xendevs);
/* ------------------------------------------------------------- */

8
hw/xenpv/xen_domainbuild.c
View File

@ -27,11 +27,11 @@ static int xenstore_domain_mkdir(char *path)
if (!xs_mkdir(xenstore, 0, path)) {
fprintf(stderr, "%s: xs_mkdir %s: failed\n", __func__, path);
return -1;
return -1;
}
if (!xs_set_permissions(xenstore, 0, path, perms_ro, 2)) {
fprintf(stderr, "%s: xs_set_permissions failed\n", __func__);
return -1;
return -1;
}
for (i = 0; writable[i]; i++) {
@ -82,8 +82,8 @@ int xenstore_domain_init1(const char *kernel, const char *ramdisk,
/* cpus */
for (i = 0; i < smp_cpus; i++) {
snprintf(path, sizeof(path), "cpu/%d/availability",i);
xenstore_write_str(dom, path, "online");
snprintf(path, sizeof(path), "cpu/%d/availability",i);
xenstore_write_str(dom, path, "online");
}
xenstore_write_int(vm, "vcpu_avail", smp_cpus);
xenstore_write_int(vm, "vcpus", smp_cpus);

10
include/elf.h
View File

@ -782,11 +782,11 @@ typedef struct {
/* ARM-specific values for sh_flags */
#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */
#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined
in the input to a link step */
in the input to a link step */
/* ARM-specific program header flags */
#define PF_ARM_SB 0x10000000 /* Segment contains the location
addressed by the static base */
addressed by the static base */
/* ARM relocs. */
#define R_ARM_NONE 0 /* No reloc */
@ -1047,7 +1047,7 @@ typedef struct {
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
#define R_X86_64_RELATIVE 8 /* Adjust by program base */
#define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative
offset to GOT */
offset to GOT */
#define R_X86_64_32 10 /* Direct 32 bit zero extended */
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
#define R_X86_64_16 12 /* Direct 16 bit zero extended */
@ -1070,7 +1070,7 @@ typedef struct {
#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */
#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */
#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch
prediction. */
prediction. */
#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */
#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */
@ -1083,7 +1083,7 @@ typedef struct {
/* Additional section indeces. */
#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared
symbols in ANSI C. */
symbols in ANSI C. */
#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */
/* Legal values for sh_type field of Elf32_Shdr. */

6
include/exec/memory.h
View File

@ -379,9 +379,9 @@ struct MemoryRegion {
MemoryRegion *alias;
hwaddr alias_offset;
int32_t priority;
QTAILQ_HEAD(subregions, MemoryRegion) subregions;
QTAILQ_HEAD(, MemoryRegion) subregions;
QTAILQ_ENTRY(MemoryRegion) subregions_link;
QTAILQ_HEAD(coalesced_ranges, CoalescedMemoryRange) coalesced;
QTAILQ_HEAD(, CoalescedMemoryRange) coalesced;
const char *name;
unsigned ioeventfd_nb;
MemoryRegionIoeventfd *ioeventfds;
@ -445,7 +445,7 @@ struct AddressSpace {
int ioeventfd_nb;
struct MemoryRegionIoeventfd *ioeventfds;
QTAILQ_HEAD(memory_listeners_as, MemoryListener) listeners;
QTAILQ_HEAD(, MemoryListener) listeners;
QTAILQ_ENTRY(AddressSpace) address_spaces_link;
};

14
include/hw/acpi/acpi.h
View File

@ -69,13 +69,13 @@
#define ACPI_BITMASK_WAKE_STATUS 0x8000
#define ACPI_BITMASK_ALL_FIXED_STATUS (\
ACPI_BITMASK_TIMER_STATUS | \
ACPI_BITMASK_BUS_MASTER_STATUS | \
ACPI_BITMASK_GLOBAL_LOCK_STATUS | \
ACPI_BITMASK_POWER_BUTTON_STATUS | \
ACPI_BITMASK_SLEEP_BUTTON_STATUS | \
ACPI_BITMASK_RT_CLOCK_STATUS | \
ACPI_BITMASK_WAKE_STATUS)
ACPI_BITMASK_TIMER_STATUS | \
ACPI_BITMASK_BUS_MASTER_STATUS | \
ACPI_BITMASK_GLOBAL_LOCK_STATUS | \
ACPI_BITMASK_POWER_BUTTON_STATUS | \
ACPI_BITMASK_SLEEP_BUTTON_STATUS | \
ACPI_BITMASK_RT_CLOCK_STATUS | \
ACPI_BITMASK_WAKE_STATUS)
/* PM1x_EN */
#define ACPI_BITMASK_TIMER_ENABLE 0x0001

2
include/hw/elf_ops.h
View File

@ -343,7 +343,7 @@ static int glue(load_elf, SZ)(const char *name, int fd,
}
if (pentry)
*pentry = (uint64_t)(elf_sword)ehdr.e_entry;
*pentry = (uint64_t)(elf_sword)ehdr.e_entry;
glue(load_symbols, SZ)(&ehdr, fd, must_swab, clear_lsb, sym_cb);

2
include/hw/ide/internal.h
View File

@ -342,7 +342,7 @@ enum ide_dma_cmd {
extern const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT];
#define ide_cmd_is_read(s) \
((s)->dma_cmd == IDE_DMA_READ)
((s)->dma_cmd == IDE_DMA_READ)
typedef struct IDEBufferedRequest {
QLIST_ENTRY(IDEBufferedRequest) list;

2
include/hw/qdev-core.h
View File

@ -206,7 +206,7 @@ struct BusState {
HotplugHandler *hotplug_handler;
int max_index;
bool realized;
QTAILQ_HEAD(ChildrenHead, BusChild) children;
QTAILQ_HEAD(, BusChild) children;
QLIST_ENTRY(BusState) sibling;
};

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