hw/arm/smmuv3: add support for stage 1 access fault
An access fault is raised when the Access Flag is not set in the looked-up PTE and the AFFD field is not set in the corresponding context descriptor. This was already implemented for stage 2. Implement it for stage 1 as well. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Mostafa Saleh <smostafa@google.com> Message-id: 20240213082211.3330400-1-luc.michel@amd.com [PMM: tweaked comment text] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -364,6 +364,17 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
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pte_addr, pte, iova, gpa,
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block_size >> 20);
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}
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/*
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* QEMU does not currently implement HTTU, so if AFFD and PTE.AF
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* are 0 we take an Access flag fault. (5.4. Context Descriptor)
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* An Access flag fault takes priority over a Permission fault.
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*/
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if (!PTE_AF(pte) && !cfg->affd) {
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info->type = SMMU_PTW_ERR_ACCESS;
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goto error;
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}
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ap = PTE_AP(pte);
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if (is_permission_fault(ap, perm)) {
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info->type = SMMU_PTW_ERR_PERMISSION;
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@ -624,6 +624,7 @@ static inline int pa_range(STE *ste)
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#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
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#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
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#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
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#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
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#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
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#define CD_HD(x) extract32((x)->word[1], 10 , 1)
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#define CD_HA(x) extract32((x)->word[1], 11 , 1)
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@ -684,6 +684,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
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cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
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cfg->tbi = CD_TBI(cd);
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cfg->asid = CD_ASID(cd);
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cfg->affd = CD_AFFD(cd);
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trace_smmuv3_decode_cd(cfg->oas);
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@ -92,6 +92,7 @@ typedef struct SMMUTransCfg {
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bool disabled; /* smmu is disabled */
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bool bypassed; /* translation is bypassed */
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bool aborted; /* translation is aborted */
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bool affd; /* AF fault disable */
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uint32_t iotlb_hits; /* counts IOTLB hits */
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uint32_t iotlb_misses; /* counts IOTLB misses*/
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/* Used by stage-1 only. */
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