target/arm: Introduce add_reg_for_lit
Provide a common routine for the places that require ALIGN(PC, 4) as the base address as opposed to plain PC. The two are always the same for A32, but the difference is meaningful for thumb mode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190807045335.1361-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
fdbcf6329d
commit
16e0d8234e
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@ -941,14 +941,8 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
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offset = -offset;
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}
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if (s->thumb && a->rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, a->rn);
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}
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tcg_gen_addi_i32(addr, addr, offset);
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/* For thumb, use of PC is UNPREDICTABLE. */
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addr = add_reg_for_lit(s, a->rn, offset);
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tmp = tcg_temp_new_i32();
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if (a->l) {
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gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
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@ -983,14 +977,8 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
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offset = -offset;
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}
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if (s->thumb && a->rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, a->rn);
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}
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tcg_gen_addi_i32(addr, addr, offset);
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/* For thumb, use of PC is UNPREDICTABLE. */
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addr = add_reg_for_lit(s, a->rn, offset);
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tmp = tcg_temp_new_i64();
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if (a->l) {
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gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
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@ -1029,13 +1017,8 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
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return true;
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}
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if (s->thumb && a->rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, a->rn);
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}
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/* For thumb, use of PC is UNPREDICTABLE. */
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addr = add_reg_for_lit(s, a->rn, 0);
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if (a->p) {
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/* pre-decrement */
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tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
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@ -1112,13 +1095,8 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
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return true;
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}
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if (s->thumb && a->rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, a->rn);
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}
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/* For thumb, use of PC is UNPREDICTABLE. */
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addr = add_reg_for_lit(s, a->rn, 0);
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if (a->p) {
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/* pre-decrement */
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tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
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@ -220,6 +220,23 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
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return tmp;
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}
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/*
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* Create a new temp, REG + OFS, except PC is ALIGN(PC, 4).
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* This is used for load/store for which use of PC implies (literal),
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* or ADD that implies ADR.
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*/
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static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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if (reg == 15) {
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tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs);
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} else {
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tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
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}
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return tmp;
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}
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/* Set a CPU register. The source must be a temporary and will be
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marked as dead. */
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static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
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@ -9457,16 +9474,12 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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*/
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bool wback = extract32(insn, 21, 1);
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if (rn == 15) {
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if (insn & (1 << 21)) {
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/* UNPREDICTABLE */
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goto illegal_op;
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}
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~3);
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} else {
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addr = load_reg(s, rn);
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if (rn == 15 && (insn & (1 << 21))) {
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/* UNPREDICTABLE */
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goto illegal_op;
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}
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addr = add_reg_for_lit(s, rn, 0);
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offset = (insn & 0xff) * 4;
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if ((insn & (1 << 23)) == 0) {
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offset = -offset;
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@ -10667,27 +10680,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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store_reg(s, rd, tmp);
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} else {
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/* Add/sub 12-bit immediate. */
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if (rn == 15) {
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offset = s->pc & ~(uint32_t)3;
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if (insn & (1 << 23))
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offset -= imm;
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else
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offset += imm;
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tmp = tcg_temp_new_i32();
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tcg_gen_movi_i32(tmp, offset);
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store_reg(s, rd, tmp);
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if (insn & (1 << 23)) {
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imm = -imm;
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}
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tmp = add_reg_for_lit(s, rn, imm);
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if (rn == 13 && rd == 13) {
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/* ADD SP, SP, imm or SUB SP, SP, imm */
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store_sp_checked(s, tmp);
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} else {
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tmp = load_reg(s, rn);
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if (insn & (1 << 23))
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tcg_gen_subi_i32(tmp, tmp, imm);
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else
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tcg_gen_addi_i32(tmp, tmp, imm);
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if (rn == 13 && rd == 13) {
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/* ADD SP, SP, imm or SUB SP, SP, imm */
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store_sp_checked(s, tmp);
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} else {
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store_reg(s, rd, tmp);
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}
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store_reg(s, rd, tmp);
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}
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}
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}
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@ -10801,61 +10802,53 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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}
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}
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memidx = get_mem_index(s);
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if (rn == 15) {
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addr = tcg_temp_new_i32();
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/* PC relative. */
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/* s->pc has already been incremented by 4. */
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imm = s->pc & 0xfffffffc;
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if (insn & (1 << 23))
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imm += insn & 0xfff;
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else
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imm -= insn & 0xfff;
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tcg_gen_movi_i32(addr, imm);
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imm = insn & 0xfff;
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if (insn & (1 << 23)) {
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/* PC relative or Positive offset. */
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addr = add_reg_for_lit(s, rn, imm);
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} else if (rn == 15) {
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/* PC relative with negative offset. */
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addr = add_reg_for_lit(s, rn, -imm);
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} else {
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addr = load_reg(s, rn);
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if (insn & (1 << 23)) {
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/* Positive offset. */
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imm = insn & 0xfff;
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tcg_gen_addi_i32(addr, addr, imm);
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} else {
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imm = insn & 0xff;
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switch ((insn >> 8) & 0xf) {
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case 0x0: /* Shifted Register. */
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shift = (insn >> 4) & 0xf;
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if (shift > 3) {
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tcg_temp_free_i32(addr);
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goto illegal_op;
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}
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tmp = load_reg(s, rm);
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if (shift)
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tcg_gen_shli_i32(tmp, tmp, shift);
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tcg_gen_add_i32(addr, addr, tmp);
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tcg_temp_free_i32(tmp);
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break;
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case 0xc: /* Negative offset. */
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tcg_gen_addi_i32(addr, addr, -imm);
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break;
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case 0xe: /* User privilege. */
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tcg_gen_addi_i32(addr, addr, imm);
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memidx = get_a32_user_mem_index(s);
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break;
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case 0x9: /* Post-decrement. */
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imm = -imm;
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/* Fall through. */
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case 0xb: /* Post-increment. */
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postinc = 1;
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writeback = 1;
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break;
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case 0xd: /* Pre-decrement. */
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imm = -imm;
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/* Fall through. */
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case 0xf: /* Pre-increment. */
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writeback = 1;
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break;
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default:
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imm = insn & 0xff;
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switch ((insn >> 8) & 0xf) {
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case 0x0: /* Shifted Register. */
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shift = (insn >> 4) & 0xf;
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if (shift > 3) {
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tcg_temp_free_i32(addr);
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goto illegal_op;
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}
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tmp = load_reg(s, rm);
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if (shift) {
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tcg_gen_shli_i32(tmp, tmp, shift);
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}
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tcg_gen_add_i32(addr, addr, tmp);
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tcg_temp_free_i32(tmp);
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break;
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case 0xc: /* Negative offset. */
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tcg_gen_addi_i32(addr, addr, -imm);
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break;
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case 0xe: /* User privilege. */
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tcg_gen_addi_i32(addr, addr, imm);
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memidx = get_a32_user_mem_index(s);
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break;
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case 0x9: /* Post-decrement. */
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imm = -imm;
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/* Fall through. */
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case 0xb: /* Post-increment. */
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postinc = 1;
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writeback = 1;
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break;
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case 0xd: /* Pre-decrement. */
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imm = -imm;
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/* Fall through. */
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case 0xf: /* Pre-increment. */
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writeback = 1;
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break;
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default:
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tcg_temp_free_i32(addr);
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goto illegal_op;
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}
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}
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@ -11051,10 +11044,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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if (insn & (1 << 11)) {
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rd = (insn >> 8) & 7;
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/* load pc-relative. Bit 1 of PC is ignored. */
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val = read_pc(s) + ((insn & 0xff) * 4);
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val &= ~(uint32_t)2;
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, val);
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addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);
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tmp = tcg_temp_new_i32();
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gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
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rd | ISSIs16Bit);
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@ -11432,16 +11422,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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* - Add PC/SP (immediate)
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*/
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rd = (insn >> 8) & 7;
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if (insn & (1 << 11)) {
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/* SP */
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tmp = load_reg(s, 13);
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} else {
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/* PC. bit 1 is ignored. */
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tmp = tcg_temp_new_i32();
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tcg_gen_movi_i32(tmp, read_pc(s) & ~(uint32_t)2);
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}
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val = (insn & 0xff) * 4;
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tcg_gen_addi_i32(tmp, tmp, val);
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tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
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store_reg(s, rd, tmp);
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break;
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