i8257: implement the IsaDma interface
Rewrite the global DMA_*() functions to use the IsaDma interface. Note that these functions will be deleted in a few commits. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-id: 1453843944-26833-12-git-send-email-hpoussin@reactos.org Signed-off-by: John Snow <jsnow@redhat.com>
This commit is contained in:
Hervé Poussineau
John Snow
parent
5484f30b2c
commit
16ffe36360
152
hw/dma/i8257.c
152
hw/dma/i8257.c
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@ -45,8 +45,6 @@
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#define ADDR 0
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#define COUNT 1
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static I8257State *dma_controllers[2];
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enum {
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CMD_MEMORY_TO_MEMORY = 0x01,
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CMD_FIXED_ADDRESS = 0x02,
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@ -289,31 +287,36 @@ static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size)
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return val;
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}
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int DMA_get_channel_mode (int nchan)
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static IsaDmaTransferMode i8257_dma_get_transfer_mode(IsaDma *obj, int nchan)
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{
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return dma_controllers[nchan > 3]->regs[nchan & 3].mode;
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I8257State *d = I8257(obj);
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return (d->regs[nchan & 3].mode >> 2) & 3;
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}
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void DMA_hold_DREQ (int nchan)
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static bool i8257_dma_has_autoinitialization(IsaDma *obj, int nchan)
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{
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int ncont, ichan;
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ncont = nchan > 3;
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ichan = nchan & 3;
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linfo ("held cont=%d chan=%d\n", ncont, ichan);
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dma_controllers[ncont]->status |= 1 << (ichan + 4);
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i8257_dma_run(dma_controllers[ncont]);
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I8257State *d = I8257(obj);
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return (d->regs[nchan & 3].mode >> 4) & 1;
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}
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void DMA_release_DREQ (int nchan)
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static void i8257_dma_hold_DREQ(IsaDma *obj, int nchan)
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{
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int ncont, ichan;
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I8257State *d = I8257(obj);
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int ichan;
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ncont = nchan > 3;
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ichan = nchan & 3;
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linfo ("released cont=%d chan=%d\n", ncont, ichan);
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dma_controllers[ncont]->status &= ~(1 << (ichan + 4));
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i8257_dma_run(dma_controllers[ncont]);
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d->status |= 1 << (ichan + 4);
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i8257_dma_run(d);
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}
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static void i8257_dma_release_DREQ(IsaDma *obj, int nchan)
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{
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I8257State *d = I8257(obj);
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int ichan;
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ichan = nchan & 3;
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d->status &= ~(1 << (ichan + 4));
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i8257_dma_run(d);
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}
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static void i8257_channel_run(I8257State *d, int ichan)
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@ -373,24 +376,26 @@ out:
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}
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}
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void DMA_register_channel (int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque)
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static void i8257_dma_register_channel(IsaDma *obj, int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque)
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{
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I8257State *d = I8257(obj);
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I8257Regs *r;
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int ichan, ncont;
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int ichan;
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ncont = nchan > 3;
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ichan = nchan & 3;
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r = dma_controllers[ncont]->regs + ichan;
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r = d->regs + ichan;
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r->transfer_handler = transfer_handler;
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r->opaque = opaque;
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}
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int DMA_read_memory (int nchan, void *buf, int pos, int len)
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static int i8257_dma_read_memory(IsaDma *obj, int nchan, void *buf, int pos,
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int len)
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{
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I8257Regs *r = &dma_controllers[nchan > 3]->regs[nchan & 3];
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I8257State *d = I8257(obj);
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I8257Regs *r = &d->regs[nchan & 3];
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hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
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if (r->mode & 0x20) {
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@ -410,9 +415,11 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
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return len;
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}
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int DMA_write_memory (int nchan, void *buf, int pos, int len)
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static int i8257_dma_write_memory(IsaDma *obj, int nchan, void *buf, int pos,
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int len)
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{
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I8257Regs *r = &dma_controllers[nchan > 3]->regs[nchan & 3];
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I8257State *s = I8257(obj);
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I8257Regs *r = &s->regs[nchan & 3];
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hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
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if (r->mode & 0x20) {
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@ -435,10 +442,10 @@ int DMA_write_memory (int nchan, void *buf, int pos, int len)
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/* request the emulator to transfer a new DMA memory block ASAP (even
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* if the idle bottom half would not have exited the iothread yet).
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*/
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void DMA_schedule(void)
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static void i8257_dma_schedule(IsaDma *obj)
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{
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if (dma_controllers[0]->dma_bh_scheduled ||
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dma_controllers[1]->dma_bh_scheduled) {
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I8257State *d = I8257(obj);
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if (d->dma_bh_scheduled) {
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qemu_notify_event();
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}
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}
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@ -572,11 +579,85 @@ static Property i8257_properties[] = {
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static void i8257_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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IsaDmaClass *idc = ISADMA_CLASS(klass);
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dc->realize = i8257_realize;
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dc->reset = i8257_reset;
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dc->vmsd = &vmstate_i8257;
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dc->props = i8257_properties;
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idc->get_transfer_mode = i8257_dma_get_transfer_mode;
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idc->has_autoinitialization = i8257_dma_has_autoinitialization;
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idc->read_memory = i8257_dma_read_memory;
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idc->write_memory = i8257_dma_write_memory;
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idc->hold_DREQ = i8257_dma_hold_DREQ;
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idc->release_DREQ = i8257_dma_release_DREQ;
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idc->schedule = i8257_dma_schedule;
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idc->register_channel = i8257_dma_register_channel;
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}
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static ISABus *i8257_bus;
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int DMA_get_channel_mode(int nchan)
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{
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IsaDma *dma = isa_get_dma(i8257_bus, nchan);
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IsaDmaClass *k = ISADMA_GET_CLASS(dma);
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uint8_t res = 0;
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res |= k->has_autoinitialization(dma, nchan) ? 0 : 0x10;
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res |= k->get_transfer_mode(dma, nchan) << 2;
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return res;
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}
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int DMA_read_memory(int nchan, void *buf, int pos, int size)
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{
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IsaDma *dma = isa_get_dma(i8257_bus, nchan);
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IsaDmaClass *k = ISADMA_GET_CLASS(dma);
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return k->read_memory(dma, nchan, buf, pos, size);
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}
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int DMA_write_memory(int nchan, void *buf, int pos, int size)
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{
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IsaDma *dma = isa_get_dma(i8257_bus, nchan);
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IsaDmaClass *k = ISADMA_GET_CLASS(dma);
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return k->write_memory(dma, nchan, buf, pos, size);
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}
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void DMA_hold_DREQ(int nchan)
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{
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IsaDma *dma = isa_get_dma(i8257_bus, nchan);
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IsaDmaClass *k = ISADMA_GET_CLASS(dma);
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k->hold_DREQ(dma, nchan);
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}
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void DMA_release_DREQ(int nchan)
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{
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IsaDma *dma = isa_get_dma(i8257_bus, nchan);
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IsaDmaClass *k = ISADMA_GET_CLASS(dma);
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k->release_DREQ(dma, nchan);
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}
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void DMA_schedule(void)
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{
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IsaDma *dma;
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IsaDmaClass *k;
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int i;
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for (i = 0; i < 2; i++) {
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dma = isa_get_dma(i8257_bus, i << 2);
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k = ISADMA_GET_CLASS(dma);
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k->schedule(dma);
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}
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}
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void DMA_register_channel(int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque)
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{
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IsaDma *dma = isa_get_dma(i8257_bus, nchan);
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IsaDmaClass *k = ISADMA_GET_CLASS(dma);
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k->register_channel(dma, nchan, transfer_handler, opaque);
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}
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static const TypeInfo i8257_info = {
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@ -584,6 +665,10 @@ static const TypeInfo i8257_info = {
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(I8257State),
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.class_init = i8257_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_ISADMA },
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{ }
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}
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};
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static void i8257_register_types(void)
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@ -605,7 +690,6 @@ void DMA_init(ISABus *bus, int high_page_enable)
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qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1);
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qdev_prop_set_int32(d, "dshift", 0);
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qdev_init_nofail(d);
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dma_controllers[0] = I8257(d);
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isa2 = isa_create(bus, TYPE_I8257);
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d = DEVICE(isa2);
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@ -614,5 +698,7 @@ void DMA_init(ISABus *bus, int high_page_enable)
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qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1);
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qdev_prop_set_int32(d, "dshift", 1);
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qdev_init_nofail(d);
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dma_controllers[1] = I8257(d);
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isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2));
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i8257_bus = bus;
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}
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