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target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present

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If the floating point extension is present, then the SG instruction
must clear the CONTROL_S.SFPA bit. Implement this.

(On a no-FPU system the bit will always be zero, so we don't need
to make the clearing of the bit conditional on ARM_FEATURE_VFP.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-8-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2019-04-29 17:35:59 +01:00
parent 8859ba3c96
commit 1702071302
1 changed files with 1 additions and 0 deletions
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target/arm/helper.c
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@ -8804,6 +8804,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
", executing it\n", env->regs[15]); ", executing it\n", env->regs[15]);
env->regs[14] &= ~1; env->regs[14] &= ~1;
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
switch_v7m_security_state(env, true); switch_v7m_security_state(env, true);
xpsr_write(env, 0, XPSR_IT); xpsr_write(env, 0, XPSR_IT);
env->regs[15] += 4; env->regs[15] += 4;