target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0, MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their AArch32 equivalents). This trapping is independent of whether fine-grained traps are enabled or not. Implement these extra traps. (We don't implement DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org
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@ -599,6 +599,33 @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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return CP_ACCESS_OK;
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}
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}
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/*
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* Check for traps to Debug Comms Channel registers. If FEAT_FGT
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* is implemented then these are controlled by MDCR_EL2.TDCC for
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* EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
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* the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
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*/
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static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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int el = arm_current_el(env);
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uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
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bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
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(arm_hcr_el2_eff(env) & HCR_TGE);
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bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
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(mdcr_el2 & MDCR_TDCC);
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bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
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(env->cp15.mdcr_el3 & MDCR_TDCC);
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if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
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return CP_ACCESS_TRAP_EL2;
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}
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if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
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return CP_ACCESS_TRAP_EL3;
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}
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return CP_ACCESS_OK;
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}
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static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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uint64_t value)
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{
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{
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@ -681,7 +708,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
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*/
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*/
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{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
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{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
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.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
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.access = PL0_R, .accessfn = access_tda,
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.access = PL0_R, .accessfn = access_tdcc,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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.type = ARM_CP_CONST, .resetvalue = 0 },
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/*
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/*
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* OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
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* OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
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@ -689,11 +716,11 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
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*/
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*/
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{ .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
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{ .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
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.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
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.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
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.access = PL1_RW, .accessfn = access_tda,
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.access = PL1_RW, .accessfn = access_tdcc,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
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{ .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
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.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
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.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
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.access = PL1_RW, .accessfn = access_tda,
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.access = PL1_RW, .accessfn = access_tdcc,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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.type = ARM_CP_CONST, .resetvalue = 0 },
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/*
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/*
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* OSECCR_EL1 provides a mechanism for an operating system
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* OSECCR_EL1 provides a mechanism for an operating system
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@ -757,7 +784,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
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*/
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*/
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{ .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
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{ .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tda,
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.access = PL1_RW, .accessfn = access_tdcc,
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.type = ARM_CP_NOP },
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.type = ARM_CP_NOP },
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/*
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/*
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* Dummy DBGCLAIM registers.
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* Dummy DBGCLAIM registers.
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