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lm32: translation routines

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This patch adds the main translation routine. All opcodes of the
LatticeMico32 processor are supported and translated to TCG ops.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Michael Walle 2011-02-17 23:45:03 +01:00 committed by Edgar E. Iglesias
parent 81ea0e1304
commit 17c0fa3d57
3 changed files with 1654 additions and 0 deletions
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259
target-lm32/helper.c Normal file
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/*
* LatticeMico32 helper routines.
*
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include "config.h"
#include "cpu.h"
#include "exec-all.h"
#include "host-utils.h"
int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
{
int prot;
address &= TARGET_PAGE_MASK;
prot = PAGE_BITS;
if (env->flags & LM32_FLAG_IGNORE_MSB) {
tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
TARGET_PAGE_SIZE);
} else {
tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
}
return 0;
}
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr & TARGET_PAGE_MASK;
}
void do_interrupt(CPUState *env)
{
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%x type=%x\n", env->pc, env->exception_index);
switch (env->exception_index) {
case EXCP_INSN_BUS_ERROR:
case EXCP_DATA_BUS_ERROR:
case EXCP_DIVIDE_BY_ZERO:
case EXCP_IRQ:
case EXCP_SYSTEMCALL:
/* non-debug exceptions */
env->regs[R_EA] = env->pc;
env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
env->ie &= ~IE_IE;
if (env->dc & DC_RE) {
env->pc = env->deba + (env->exception_index * 32);
} else {
env->pc = env->eba + (env->exception_index * 32);
}
log_cpu_state_mask(CPU_LOG_INT, env, 0);
break;
case EXCP_BREAKPOINT:
case EXCP_WATCHPOINT:
/* debug exceptions */
env->regs[R_BA] = env->pc;
env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
env->ie &= ~IE_IE;
if (env->dc & DC_RE) {
env->pc = env->deba + (env->exception_index * 32);
} else {
env->pc = env->eba + (env->exception_index * 32);
}
log_cpu_state_mask(CPU_LOG_INT, env, 0);
break;
default:
cpu_abort(env, "unhandled exception type=%d\n",
env->exception_index);
break;
}
}
typedef struct {
const char *name;
uint32_t revision;
uint8_t num_interrupts;
uint8_t num_breakpoints;
uint8_t num_watchpoints;
uint32_t features;
} LM32Def;
static const LM32Def lm32_defs[] = {
{
.name = "lm32-basic",
.revision = 3,
.num_interrupts = 32,
.num_breakpoints = 4,
.num_watchpoints = 4,
.features = (LM32_FEATURE_SHIFT
| LM32_FEATURE_SIGN_EXTEND
| LM32_FEATURE_CYCLE_COUNT),
},
{
.name = "lm32-standard",
.revision = 3,
.num_interrupts = 32,
.num_breakpoints = 4,
.num_watchpoints = 4,
.features = (LM32_FEATURE_MULTIPLY
| LM32_FEATURE_DIVIDE
| LM32_FEATURE_SHIFT
| LM32_FEATURE_SIGN_EXTEND
| LM32_FEATURE_I_CACHE
| LM32_FEATURE_CYCLE_COUNT),
},
{
.name = "lm32-full",
.revision = 3,
.num_interrupts = 32,
.num_breakpoints = 4,
.num_watchpoints = 4,
.features = (LM32_FEATURE_MULTIPLY
| LM32_FEATURE_DIVIDE
| LM32_FEATURE_SHIFT
| LM32_FEATURE_SIGN_EXTEND
| LM32_FEATURE_I_CACHE
| LM32_FEATURE_D_CACHE
| LM32_FEATURE_CYCLE_COUNT),
}
};
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
{
int i;
cpu_fprintf(f, "Available CPUs:\n");
for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
cpu_fprintf(f, " %s\n", lm32_defs[i].name);
}
}
static const LM32Def *cpu_lm32_find_by_name(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
if (strcasecmp(name, lm32_defs[i].name) == 0) {
return &lm32_defs[i];
}
}
return NULL;
}
static uint32_t cfg_by_def(const LM32Def *def)
{
uint32_t cfg = 0;
if (def->features & LM32_FEATURE_MULTIPLY) {
cfg |= CFG_M;
}
if (def->features & LM32_FEATURE_DIVIDE) {
cfg |= CFG_D;
}
if (def->features & LM32_FEATURE_SHIFT) {
cfg |= CFG_S;
}
if (def->features & LM32_FEATURE_SIGN_EXTEND) {
cfg |= CFG_X;
}
if (def->features & LM32_FEATURE_I_CACHE) {
cfg |= CFG_IC;
}
if (def->features & LM32_FEATURE_D_CACHE) {
cfg |= CFG_DC;
}
if (def->features & LM32_FEATURE_CYCLE_COUNT) {
cfg |= CFG_CC;
}
cfg |= (def->num_interrupts << CFG_INT_SHIFT);
cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
cfg |= (def->revision << CFG_REV_SHIFT);
return cfg;
}
CPUState *cpu_lm32_init(const char *cpu_model)
{
CPUState *env;
const LM32Def *def;
static int tcg_initialized;
def = cpu_lm32_find_by_name(cpu_model);
if (!def) {
return NULL;
}
env = qemu_mallocz(sizeof(CPUState));
env->features = def->features;
env->num_bps = def->num_breakpoints;
env->num_wps = def->num_watchpoints;
env->cfg = cfg_by_def(def);
env->flags = 0;
cpu_exec_init(env);
cpu_reset(env);
if (!tcg_initialized) {
tcg_initialized = 1;
lm32_translate_init();
}
return env;
}
/* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
* area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
* 0x80000000-0xffffffff is not cached and used to access IO devices. */
void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
{
if (value) {
env->flags |= LM32_FLAG_IGNORE_MSB;
} else {
env->flags &= ~LM32_FLAG_IGNORE_MSB;
}
}
void cpu_reset(CPUState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
log_cpu_state(env, 0);
}
tlb_flush(env, 1);
/* reset cpu state */
memset(env, 0, offsetof(CPULM32State, breakpoints));
}

78
target-lm32/lm32-decode.h Normal file
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/*
* LatticeMico32 instruction decoding macros.
*
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/* Convenient binary macros */
#define HEX__(n) 0x##n##LU
#define B8__(x) (((x&0x0000000FLU) ? 1 : 0) \
+ ((x&0x000000F0LU) ? 2 : 0) \
+ ((x&0x00000F00LU) ? 4 : 0) \
+ ((x&0x0000F000LU) ? 8 : 0) \
+ ((x&0x000F0000LU) ? 16 : 0) \
+ ((x&0x00F00000LU) ? 32 : 0) \
+ ((x&0x0F000000LU) ? 64 : 0) \
+ ((x&0xF0000000LU) ? 128 : 0))
#define B8(d) ((unsigned char)B8__(HEX__(d)))
/* Decode logic, value and mask. */
#define DEC_ADD {B8(00001101), B8(00011111)}
#define DEC_AND {B8(00001000), B8(00011111)}
#define DEC_ANDHI {B8(00011000), B8(00111111)}
#define DEC_B {B8(00110000), B8(00111111)}
#define DEC_BI {B8(00111000), B8(00111111)}
#define DEC_BE {B8(00010001), B8(00111111)}
#define DEC_BG {B8(00010010), B8(00111111)}
#define DEC_BGE {B8(00010011), B8(00111111)}
#define DEC_BGEU {B8(00010100), B8(00111111)}
#define DEC_BGU {B8(00010101), B8(00111111)}
#define DEC_BNE {B8(00010111), B8(00111111)}
#define DEC_CALL {B8(00110110), B8(00111111)}
#define DEC_CALLI {B8(00111110), B8(00111111)}
#define DEC_CMPE {B8(00011001), B8(00011111)}
#define DEC_CMPG {B8(00011010), B8(00011111)}
#define DEC_CMPGE {B8(00011011), B8(00011111)}
#define DEC_CMPGEU {B8(00011100), B8(00011111)}
#define DEC_CMPGU {B8(00011101), B8(00011111)}
#define DEC_CMPNE {B8(00011111), B8(00011111)}
#define DEC_DIVU {B8(00100011), B8(00111111)}
#define DEC_LB {B8(00000100), B8(00111111)}
#define DEC_LBU {B8(00010000), B8(00111111)}
#define DEC_LH {B8(00000111), B8(00111111)}
#define DEC_LHU {B8(00001011), B8(00111111)}
#define DEC_LW {B8(00001010), B8(00111111)}
#define DEC_MODU {B8(00110001), B8(00111111)}
#define DEC_MUL {B8(00000010), B8(00011111)}
#define DEC_NOR {B8(00000001), B8(00011111)}
#define DEC_OR {B8(00001110), B8(00011111)}
#define DEC_ORHI {B8(00011110), B8(00111111)}
#define DEC_RAISE {B8(00101011), B8(00111111)}
#define DEC_RCSR {B8(00100100), B8(00111111)}
#define DEC_SB {B8(00001100), B8(00111111)}
#define DEC_SEXTB {B8(00101100), B8(00111111)}
#define DEC_SEXTH {B8(00110111), B8(00111111)}
#define DEC_SH {B8(00000011), B8(00111111)}
#define DEC_SL {B8(00001111), B8(00011111)}
#define DEC_SR {B8(00000101), B8(00011111)}
#define DEC_SRU {B8(00000000), B8(00011111)}
#define DEC_SUB {B8(00110010), B8(00111111)}
#define DEC_SW {B8(00010110), B8(00111111)}
#define DEC_USER {B8(00110011), B8(00111111)}
#define DEC_WCSR {B8(00110100), B8(00111111)}
#define DEC_XNOR {B8(00001001), B8(00011111)}
#define DEC_XOR {B8(00000110), B8(00011111)}

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target-lm32/translate.c Normal file
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