From a01491a238fab670ba68b5c649c109c64ae23e21 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 17 Nov 2023 11:02:39 +0100 Subject: [PATCH 1/2] target/hppa: Fix 64-bit SHRPD instruction When shifting the two joined 64-bit registers right, shift the upper 64-bit register to the left and the lower 64-bit register to the right before merging them with OR. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4a4830c3e3..3ef39b1bd7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3438,9 +3438,9 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) TCGv_i64 n = tcg_temp_new_i64(); tcg_gen_xori_i64(n, cpu_sar, 63); - tcg_gen_shl_i64(t, src2, n); + tcg_gen_shl_i64(t, src1, n); tcg_gen_shli_i64(t, t, 1); - tcg_gen_shr_i64(dest, src1, cpu_sar); + tcg_gen_shr_i64(dest, src2, cpu_sar); tcg_gen_or_i64(dest, dest, t); } else { TCGv_i64 t = tcg_temp_new_i64(); From 2f926bfd5b79e6219ae65a1e530b38f37d62b384 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 17 Nov 2023 11:26:02 +0100 Subject: [PATCH 2/2] disas/hppa: Show hexcode of instruction along with disassembly On hppa many instructions can be expressed by different bytecodes. To be able to debug qemu translation bugs it's therefore necessary to see the currently executed byte codes without the need to lookup the sequence without the full executable. With this patch the instruction byte code is shown beside the disassembly. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- disas/hppa.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/disas/hppa.c b/disas/hppa.c index dcf9a47f34..cce4f4aa37 100644 --- a/disas/hppa.c +++ b/disas/hppa.c @@ -1968,6 +1968,10 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info) insn = bfd_getb32 (buffer); + info->fprintf_func(info->stream, " %02x %02x %02x %02x ", + (insn >> 24) & 0xff, (insn >> 16) & 0xff, + (insn >> 8) & 0xff, insn & 0xff); + for (i = 0; i < NUMOPCODES; ++i) { const struct pa_opcode *opcode = &pa_opcodes[i]; @@ -2826,6 +2830,6 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info) return sizeof (insn); } } - (*info->fprintf_func) (info->stream, "#%8x", insn); + info->fprintf_func(info->stream, ""); return sizeof (insn); }