target/m68k: Avoid tcg_const_* throughout
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
7b346e4673
commit
1852ce5a70
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@ -264,10 +264,7 @@ static void gen_jmp(DisasContext *s, TCGv dest)
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static void gen_raise_exception(int nr)
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{
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TCGv_i32 tmp;
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tmp = tcg_const_i32(nr);
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gen_helper_raise_exception(cpu_env, tmp);
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gen_helper_raise_exception(cpu_env, tcg_constant_i32(nr));
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}
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static void gen_raise_exception_format2(DisasContext *s, int nr,
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@ -471,7 +468,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
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if ((ext & 0x80) == 0) {
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/* base not suppressed */
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if (IS_NULL_QREG(base)) {
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base = tcg_const_i32(offset + bd);
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base = tcg_constant_i32(offset + bd);
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bd = 0;
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}
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if (!IS_NULL_QREG(add)) {
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@ -487,7 +484,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
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add = tmp;
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}
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} else {
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add = tcg_const_i32(bd);
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add = tcg_constant_i32(bd);
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}
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if ((ext & 3) != 0) {
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/* memory indirect */
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@ -623,8 +620,7 @@ static void gen_flush_flags(DisasContext *s)
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break;
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default:
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t0 = tcg_const_i32(s->cc_op);
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gen_helper_flush_flags(cpu_env, t0);
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gen_helper_flush_flags(cpu_env, tcg_constant_i32(s->cc_op));
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s->cc_op_synced = 1;
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break;
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}
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@ -785,14 +781,14 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
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switch (reg0) {
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case 0: /* Absolute short. */
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offset = (int16_t)read_im16(env, s);
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return tcg_const_i32(offset);
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return tcg_constant_i32(offset);
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case 1: /* Absolute long. */
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offset = read_im32(env, s);
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return tcg_const_i32(offset);
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return tcg_constant_i32(offset);
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case 2: /* pc displacement */
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offset = s->pc;
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offset += (int16_t)read_im16(env, s);
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return tcg_const_i32(offset);
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return tcg_constant_i32(offset);
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case 3: /* pc index+displacement. */
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return gen_lea_indexed(env, s, NULL_QREG);
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case 4: /* Immediate. */
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@ -1167,23 +1163,23 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
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}
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switch (opsize) {
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case OS_BYTE:
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tmp = tcg_const_i32((int8_t)read_im8(env, s));
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tmp = tcg_constant_i32((int8_t)read_im8(env, s));
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gen_helper_exts32(cpu_env, fp, tmp);
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break;
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case OS_WORD:
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tmp = tcg_const_i32((int16_t)read_im16(env, s));
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tmp = tcg_constant_i32((int16_t)read_im16(env, s));
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gen_helper_exts32(cpu_env, fp, tmp);
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break;
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case OS_LONG:
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tmp = tcg_const_i32(read_im32(env, s));
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tmp = tcg_constant_i32(read_im32(env, s));
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gen_helper_exts32(cpu_env, fp, tmp);
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break;
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case OS_SINGLE:
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tmp = tcg_const_i32(read_im32(env, s));
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tmp = tcg_constant_i32(read_im32(env, s));
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gen_helper_extf32(cpu_env, fp, tmp);
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break;
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case OS_DOUBLE:
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t64 = tcg_const_i64(read_im64(env, s));
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t64 = tcg_constant_i64(read_im64(env, s));
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gen_helper_extf64(cpu_env, fp, t64);
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break;
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case OS_EXTENDED:
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@ -1191,9 +1187,9 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
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gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
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break;
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}
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tmp = tcg_const_i32(read_im32(env, s) >> 16);
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tmp = tcg_constant_i32(read_im32(env, s) >> 16);
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tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
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t64 = tcg_const_i64(read_im64(env, s));
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t64 = tcg_constant_i64(read_im64(env, s));
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tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
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break;
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case OS_PACKED:
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@ -1253,7 +1249,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
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goto done;
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case 10: /* PL */
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case 11: /* MI */
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c->v2 = tcg_const_i32(0);
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c->v2 = tcg_constant_i32(0);
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c->v1 = tmp = tcg_temp_new();
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tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
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gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
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@ -1269,7 +1265,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
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}
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}
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c->v2 = tcg_const_i32(0);
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c->v2 = tcg_constant_i32(0);
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switch (cond) {
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case 0: /* T */
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@ -2000,7 +1996,7 @@ DISAS_INSN(movem)
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addr = tcg_temp_new();
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tcg_gen_mov_i32(addr, tmp);
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incr = tcg_const_i32(opsize_bytes(opsize));
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incr = tcg_constant_i32(opsize_bytes(opsize));
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if (is_load) {
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/* memory to register */
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@ -2236,13 +2232,13 @@ DISAS_INSN(arith_im)
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opsize = insn_opsize(insn);
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switch (opsize) {
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case OS_BYTE:
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im = tcg_const_i32((int8_t)read_im8(env, s));
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im = tcg_constant_i32((int8_t)read_im8(env, s));
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break;
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case OS_WORD:
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im = tcg_const_i32((int16_t)read_im16(env, s));
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im = tcg_constant_i32((int16_t)read_im16(env, s));
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break;
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case OS_LONG:
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im = tcg_const_i32(read_im32(env, s));
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im = tcg_constant_i32(read_im32(env, s));
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break;
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default:
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g_assert_not_reached();
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@ -2394,7 +2390,6 @@ DISAS_INSN(cas2w)
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{
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uint16_t ext1, ext2;
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TCGv addr1, addr2;
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TCGv regs;
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/* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
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@ -2426,13 +2421,13 @@ DISAS_INSN(cas2w)
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* Dc2 = (R2)
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*/
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regs = tcg_const_i32(REG(ext2, 6) |
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(REG(ext1, 6) << 3) |
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(REG(ext2, 0) << 6) |
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(REG(ext1, 0) << 9));
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if (tb_cflags(s->base.tb) & CF_PARALLEL) {
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gen_helper_exit_atomic(cpu_env);
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} else {
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TCGv regs = tcg_constant_i32(REG(ext2, 6) |
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(REG(ext1, 6) << 3) |
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(REG(ext2, 0) << 6) |
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(REG(ext1, 0) << 9));
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gen_helper_cas2w(cpu_env, regs, addr1, addr2);
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}
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@ -2476,10 +2471,10 @@ DISAS_INSN(cas2l)
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* Dc2 = (R2)
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*/
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regs = tcg_const_i32(REG(ext2, 6) |
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(REG(ext1, 6) << 3) |
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(REG(ext2, 0) << 6) |
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(REG(ext1, 0) << 9));
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regs = tcg_constant_i32(REG(ext2, 6) |
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(REG(ext1, 6) << 3) |
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(REG(ext2, 0) << 6) |
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(REG(ext1, 0) << 9));
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if (tb_cflags(s->base.tb) & CF_PARALLEL) {
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gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
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} else {
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@ -2553,7 +2548,7 @@ DISAS_INSN(negx)
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* (X, N) = -(src + X);
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*/
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z = tcg_const_i32(0);
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z = tcg_constant_i32(0);
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tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
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tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
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gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
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@ -2598,8 +2593,7 @@ DISAS_INSN(clr)
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int opsize;
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TCGv zero;
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zero = tcg_const_i32(0);
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zero = tcg_constant_i32(0);
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opsize = insn_opsize(insn);
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DEST_EA(env, insn, opsize, zero, NULL);
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gen_logic_cc(s, zero, opsize);
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@ -2935,7 +2929,7 @@ DISAS_INSN(jump)
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}
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if ((insn & 0x40) == 0) {
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/* jsr */
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gen_push(s, tcg_const_i32(s->pc));
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gen_push(s, tcg_constant_i32(s->pc));
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}
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gen_jmp(s, tmp);
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}
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@ -2960,7 +2954,7 @@ DISAS_INSN(addsubq)
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if (imm == 0) {
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imm = 8;
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}
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val = tcg_const_i32(imm);
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val = tcg_constant_i32(imm);
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dest = tcg_temp_new();
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tcg_gen_mov_i32(dest, src);
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if ((insn & 0x38) == 0x08) {
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@ -3004,7 +2998,7 @@ DISAS_INSN(branch)
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}
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if (op == 1) {
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/* bsr */
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gen_push(s, tcg_const_i32(s->pc));
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gen_push(s, tcg_constant_i32(s->pc));
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}
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if (op > 1) {
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/* Bcc */
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@ -3153,9 +3147,10 @@ DISAS_INSN(mov3q)
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int val;
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val = (insn >> 9) & 7;
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if (val == 0)
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if (val == 0) {
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val = -1;
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src = tcg_const_i32(val);
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}
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src = tcg_constant_i32(val);
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gen_logic_cc(s, src, OS_LONG);
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DEST_EA(env, insn, OS_LONG, src, NULL);
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}
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@ -3433,7 +3428,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
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tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
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/* Note that C=0 if shift count is 0, and we get that for free. */
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} else {
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TCGv zero = tcg_const_i32(0);
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TCGv zero = tcg_constant_i32(0);
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tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
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tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
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tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
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@ -3455,7 +3450,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
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* V = ((s ^ t) & (-1 << (bits - 1))) != 0
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*/
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if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) {
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TCGv_i64 tt = tcg_const_i64(32);
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TCGv_i64 tt = tcg_constant_i64(32);
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/* if shift is greater than 32, use 32 */
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tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
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/* Sign extend the input to 64 bits; re-do the shift. */
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@ -3636,7 +3631,7 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
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{
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TCGv X, shl, shr, shx, sz, zero;
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sz = tcg_const_i32(size);
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sz = tcg_constant_i32(size);
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shr = tcg_temp_new();
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shl = tcg_temp_new();
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@ -3647,7 +3642,7 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
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tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
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tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
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/* shx = shx < 0 ? size : shx; */
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zero = tcg_const_i32(0);
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zero = tcg_constant_i32(0);
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tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
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} else {
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tcg_gen_mov_i32(shr, shift); /* shr = shift */
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@ -3726,7 +3721,7 @@ static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
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/* if shift == 0, register and X are not affected */
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zero = tcg_const_i32(0);
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zero = tcg_constant_i32(0);
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tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
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tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
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@ -3744,7 +3739,7 @@ DISAS_INSN(rotate_im)
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tmp = 8;
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}
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shift = tcg_const_i32(tmp);
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shift = tcg_constant_i32(tmp);
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if (insn & 8) {
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rotate(DREG(insn, 0), shift, left, 32);
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} else {
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@ -3769,7 +3764,7 @@ DISAS_INSN(rotate8_im)
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tmp = 8;
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}
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shift = tcg_const_i32(tmp);
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shift = tcg_constant_i32(tmp);
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if (insn & 8) {
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rotate(reg, shift, left, 8);
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} else {
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@ -3793,7 +3788,7 @@ DISAS_INSN(rotate16_im)
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tmp = 8;
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}
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shift = tcg_const_i32(tmp);
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shift = tcg_constant_i32(tmp);
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if (insn & 8) {
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rotate(reg, shift, left, 16);
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} else {
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@ -3908,7 +3903,7 @@ DISAS_INSN(rotate_mem)
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SRC_EA(env, src, OS_WORD, 0, &addr);
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shift = tcg_const_i32(1);
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shift = tcg_constant_i32(1);
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if (insn & 0x0200) {
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rotate(src, shift, left, 16);
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} else {
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@ -4002,12 +3997,12 @@ DISAS_INSN(bfext_mem)
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if (ext & 0x20) {
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len = DREG(ext, 0);
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} else {
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len = tcg_const_i32(extract32(ext, 0, 5));
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len = tcg_constant_i32(extract32(ext, 0, 5));
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}
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if (ext & 0x800) {
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ofs = DREG(ext, 6);
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} else {
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ofs = tcg_const_i32(extract32(ext, 6, 5));
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ofs = tcg_constant_i32(extract32(ext, 6, 5));
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}
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if (is_sign) {
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@ -4123,12 +4118,12 @@ DISAS_INSN(bfop_mem)
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if (ext & 0x20) {
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len = DREG(ext, 0);
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} else {
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len = tcg_const_i32(extract32(ext, 0, 5));
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len = tcg_constant_i32(extract32(ext, 0, 5));
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}
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if (ext & 0x800) {
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ofs = DREG(ext, 6);
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} else {
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ofs = tcg_const_i32(extract32(ext, 6, 5));
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ofs = tcg_constant_i32(extract32(ext, 6, 5));
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}
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switch (insn & 0x0f00) {
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@ -4240,12 +4235,12 @@ DISAS_INSN(bfins_mem)
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if (ext & 0x20) {
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len = DREG(ext, 0);
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} else {
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len = tcg_const_i32(extract32(ext, 0, 5));
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len = tcg_constant_i32(extract32(ext, 0, 5));
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}
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if (ext & 0x800) {
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ofs = DREG(ext, 6);
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} else {
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ofs = tcg_const_i32(extract32(ext, 6, 5));
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ofs = tcg_constant_i32(extract32(ext, 6, 5));
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}
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gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
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@ -4378,7 +4373,7 @@ DISAS_INSN(move16_mem)
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TCGv reg, addr;
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reg = AREG(insn, 0);
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addr = tcg_const_i32(read_im32(env, s));
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addr = tcg_constant_i32(read_im32(env, s));
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if ((insn >> 3) & 1) {
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/* MOVE16 (xxx).L, (Ay) */
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@ -4568,14 +4563,14 @@ DISAS_INSN(cf_movec)
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} else {
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reg = DREG(ext, 12);
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}
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gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
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gen_helper_cf_movec_to(cpu_env, tcg_constant_i32(ext & 0xfff), reg);
|
||||
gen_exit_tb(s);
|
||||
}
|
||||
|
||||
DISAS_INSN(m68k_movec)
|
||||
{
|
||||
uint16_t ext;
|
||||
TCGv reg;
|
||||
TCGv reg, creg;
|
||||
|
||||
if (IS_USER(s)) {
|
||||
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
|
||||
|
@ -4589,10 +4584,11 @@ DISAS_INSN(m68k_movec)
|
|||
} else {
|
||||
reg = DREG(ext, 12);
|
||||
}
|
||||
creg = tcg_constant_i32(ext & 0xfff);
|
||||
if (insn & 1) {
|
||||
gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
|
||||
gen_helper_m68k_movec_to(cpu_env, creg, reg);
|
||||
} else {
|
||||
gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
|
||||
gen_helper_m68k_movec_from(reg, cpu_env, creg);
|
||||
}
|
||||
gen_exit_tb(s);
|
||||
}
|
||||
|
@ -4643,7 +4639,7 @@ DISAS_INSN(pflush)
|
|||
return;
|
||||
}
|
||||
|
||||
opmode = tcg_const_i32((insn >> 3) & 3);
|
||||
opmode = tcg_constant_i32((insn >> 3) & 3);
|
||||
gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
|
||||
}
|
||||
|
||||
|
@ -4655,7 +4651,7 @@ DISAS_INSN(ptest)
|
|||
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
|
||||
return;
|
||||
}
|
||||
is_read = tcg_const_i32((insn >> 5) & 1);
|
||||
is_read = tcg_constant_i32((insn >> 5) & 1);
|
||||
gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
|
||||
}
|
||||
#endif
|
||||
|
@ -4825,7 +4821,7 @@ static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
|
|||
gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
|
||||
return;
|
||||
}
|
||||
tmp = tcg_const_i32(read_im32(env, s));
|
||||
tmp = tcg_constant_i32(read_im32(env, s));
|
||||
gen_store_fcr(s, tmp, mask);
|
||||
return;
|
||||
}
|
||||
|
@ -4962,7 +4958,7 @@ DISAS_INSN(fpu)
|
|||
case 2:
|
||||
if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
|
||||
/* fmovecr */
|
||||
TCGv rom_offset = tcg_const_i32(opmode);
|
||||
TCGv rom_offset = tcg_constant_i32(opmode);
|
||||
cpu_dest = gen_fp_ptr(REG(ext, 7));
|
||||
gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
|
||||
return;
|
||||
|
@ -5186,7 +5182,7 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
|
|||
{
|
||||
TCGv fpsr;
|
||||
|
||||
c->v2 = tcg_const_i32(0);
|
||||
c->v2 = tcg_constant_i32(0);
|
||||
/* TODO: Raise BSUN exception. */
|
||||
fpsr = tcg_temp_new();
|
||||
gen_load_fcr(s, fpsr, M68K_FPSR);
|
||||
|
@ -5406,7 +5402,7 @@ DISAS_INSN(fsave)
|
|||
|
||||
if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
|
||||
/* always write IDLE */
|
||||
TCGv idle = tcg_const_i32(0x41000000);
|
||||
TCGv idle = tcg_constant_i32(0x41000000);
|
||||
DEST_EA(env, insn, OS_LONG, idle, NULL);
|
||||
} else {
|
||||
disas_undef(env, s, insn);
|
||||
|
@ -5536,7 +5532,7 @@ DISAS_INSN(mac)
|
|||
/* Skip the accumulate if the value is already saturated. */
|
||||
l1 = gen_new_label();
|
||||
tmp = tcg_temp_new();
|
||||
gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
|
||||
gen_op_and32(tmp, QREG_MACSR, tcg_constant_i32(MACSR_PAV0 << acc));
|
||||
gen_op_jmp_nz32(tmp, l1);
|
||||
}
|
||||
#endif
|
||||
|
@ -5547,11 +5543,11 @@ DISAS_INSN(mac)
|
|||
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
|
||||
|
||||
if (s->env->macsr & MACSR_FI)
|
||||
gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
|
||||
gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
|
||||
else if (s->env->macsr & MACSR_SU)
|
||||
gen_helper_macsats(cpu_env, tcg_const_i32(acc));
|
||||
gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
|
||||
else
|
||||
gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
|
||||
gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
|
||||
|
||||
#if 0
|
||||
/* Disabled because conditional branches clobber temporary vars. */
|
||||
|
@ -5570,7 +5566,7 @@ DISAS_INSN(mac)
|
|||
/* Skip the accumulate if the value is already saturated. */
|
||||
l1 = gen_new_label();
|
||||
tmp = tcg_temp_new();
|
||||
gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
|
||||
gen_op_and32(tmp, QREG_MACSR, tcg_constant_i32(MACSR_PAV0 << acc));
|
||||
gen_op_jmp_nz32(tmp, l1);
|
||||
}
|
||||
#endif
|
||||
|
@ -5579,18 +5575,18 @@ DISAS_INSN(mac)
|
|||
else
|
||||
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
|
||||
if (s->env->macsr & MACSR_FI)
|
||||
gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
|
||||
gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
|
||||
else if (s->env->macsr & MACSR_SU)
|
||||
gen_helper_macsats(cpu_env, tcg_const_i32(acc));
|
||||
gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
|
||||
else
|
||||
gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
|
||||
gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
|
||||
#if 0
|
||||
/* Disabled because conditional branches clobber temporary vars. */
|
||||
if (l1 != -1)
|
||||
gen_set_label(l1);
|
||||
#endif
|
||||
}
|
||||
gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
|
||||
gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(acc));
|
||||
|
||||
if (insn & 0x30) {
|
||||
TCGv rw;
|
||||
|
@ -5640,8 +5636,8 @@ DISAS_INSN(move_mac)
|
|||
int src;
|
||||
TCGv dest;
|
||||
src = insn & 3;
|
||||
dest = tcg_const_i32((insn >> 9) & 3);
|
||||
gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
|
||||
dest = tcg_constant_i32((insn >> 9) & 3);
|
||||
gen_helper_mac_move(cpu_env, dest, tcg_constant_i32(src));
|
||||
gen_mac_clear_flags();
|
||||
gen_helper_mac_set_flags(cpu_env, dest);
|
||||
}
|
||||
|
@ -5666,7 +5662,7 @@ DISAS_INSN(from_mext)
|
|||
TCGv reg;
|
||||
TCGv acc;
|
||||
reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
|
||||
acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
|
||||
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
|
||||
if (s->env->macsr & MACSR_FI)
|
||||
gen_helper_get_mac_extf(reg, cpu_env, acc);
|
||||
else
|
||||
|
@ -5701,7 +5697,7 @@ DISAS_INSN(to_mac)
|
|||
}
|
||||
tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
|
||||
gen_mac_clear_flags();
|
||||
gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
|
||||
gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(accnum));
|
||||
}
|
||||
|
||||
DISAS_INSN(to_macsr)
|
||||
|
@ -5724,7 +5720,7 @@ DISAS_INSN(to_mext)
|
|||
TCGv val;
|
||||
TCGv acc;
|
||||
SRC_EA(env, val, OS_LONG, 0, NULL);
|
||||
acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
|
||||
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
|
||||
if (s->env->macsr & MACSR_FI)
|
||||
gen_helper_set_mac_extf(cpu_env, val, acc);
|
||||
else if (s->env->macsr & MACSR_SU)
|
||||
|
|
Loading…
Reference in New Issue