tcg/tci: Restrict TCG_TARGET_NB_REGS to 16
As noted in several comments, 8 regs is not enough for 32-bit to perform calls, as currently implemented. Shortly, we will rearrange the encoding which will make 32 regs impossible. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -187,7 +187,6 @@ static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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#if TCG_TARGET_NB_REGS >= 16
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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@ -196,7 +195,6 @@ static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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#endif
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};
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#if MAX_OPC_PARAM_IARGS != 6
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@ -216,15 +214,11 @@ static const int tcg_target_call_iarg_regs[] = {
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#if TCG_TARGET_REG_BITS == 32
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/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
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TCG_REG_R7,
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#if TCG_TARGET_NB_REGS >= 16
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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#else
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# error Too few input registers available
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#endif
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#endif
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};
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@ -245,7 +239,6 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"r05",
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"r06",
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"r07",
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#if TCG_TARGET_NB_REGS >= 16
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"r08",
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"r09",
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"r10",
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@ -254,25 +247,6 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"r13",
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"r14",
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"r15",
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#if TCG_TARGET_NB_REGS >= 32
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"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
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"r30",
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"r31"
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#endif
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#endif
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};
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#endif
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@ -133,11 +133,8 @@
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#define TCG_TARGET_HAS_mulu2_i32 1
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#endif /* TCG_TARGET_REG_BITS == 64 */
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/* Number of registers available.
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For 32 bit hosts, we need more than 8 registers (call arguments). */
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/* #define TCG_TARGET_NB_REGS 8 */
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/* Number of registers available. */
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#define TCG_TARGET_NB_REGS 16
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/* #define TCG_TARGET_NB_REGS 32 */
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/* List of registers which are used by TCG. */
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typedef enum {
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@ -149,7 +146,6 @@ typedef enum {
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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#if TCG_TARGET_NB_REGS >= 16
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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@ -158,33 +154,15 @@ typedef enum {
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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#if TCG_TARGET_NB_REGS >= 32
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TCG_REG_R16,
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TCG_REG_R17,
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TCG_REG_R18,
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TCG_REG_R19,
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TCG_REG_R20,
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TCG_REG_R21,
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TCG_REG_R22,
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TCG_REG_R23,
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TCG_REG_R24,
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TCG_REG_R25,
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TCG_REG_R26,
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TCG_REG_R27,
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TCG_REG_R28,
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TCG_REG_R29,
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TCG_REG_R30,
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TCG_REG_R31,
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#endif
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#endif
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TCG_AREG0 = TCG_REG_R14,
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TCG_REG_CALL_STACK = TCG_REG_R15,
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/* Special value UINT8_MAX is used by TCI to encode constant values. */
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TCG_CONST = UINT8_MAX
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} TCGReg;
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#define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
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/* Used for function call generation. */
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#define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#define TCG_TARGET_STACK_ALIGN 16
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