hw/loongarch: Improve acpi dsdt table
Cleanup the previous pci information in acpi dsdt table. And using the common acpi_dsdt_add_gpex function to build the gpex and pci information. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Acked-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220908094623.73051-10-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Xiaojuan Yang
Song Gao
parent
c3da26f314
commit
1895b96792
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@ -30,6 +30,7 @@
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#include "qom/qom-qobject.h"
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#include "hw/acpi/generic_event_device.h"
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#include "hw/pci-host/gpex.h"
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#define ACPI_BUILD_ALIGN_SIZE 0x1000
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#define ACPI_BUILD_TABLE_SIZE 0x20000
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@ -206,108 +207,6 @@ struct AcpiBuildState {
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MemoryRegion *linker_mr;
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} AcpiBuildState;
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static void build_gpex_pci0_int(Aml *table)
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{
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Aml *sb_scope = aml_scope("_SB");
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Aml *pci0_scope = aml_scope("PCI0");
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Aml *prt_pkg = aml_varpackage(128);
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int slot, pin;
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for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
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for (pin = 0; pin < PCI_NUM_PINS; pin++) {
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Aml *pkg = aml_package(4);
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aml_append(pkg, aml_int((slot << 16) | 0xFFFF));
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aml_append(pkg, aml_int(pin));
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aml_append(pkg, aml_int(0));
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aml_append(pkg, aml_int(80 + (slot + pin) % 4));
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aml_append(prt_pkg, pkg);
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}
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}
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aml_append(pci0_scope, aml_name_decl("_PRT", prt_pkg));
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aml_append(sb_scope, pci0_scope);
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aml_append(table, sb_scope);
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}
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static void build_dbg_aml(Aml *table)
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{
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Aml *field;
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Aml *method;
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Aml *while_ctx;
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Aml *scope = aml_scope("\\");
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Aml *buf = aml_local(0);
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Aml *len = aml_local(1);
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Aml *idx = aml_local(2);
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aml_append(scope,
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aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
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field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
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aml_append(field, aml_named_field("DBGB", 8));
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aml_append(scope, field);
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method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
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aml_append(method, aml_to_hexstring(aml_arg(0), buf));
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aml_append(method, aml_to_buffer(buf, buf));
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aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
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aml_append(method, aml_store(aml_int(0), idx));
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while_ctx = aml_while(aml_lless(idx, len));
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aml_append(while_ctx,
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aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
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aml_append(while_ctx, aml_increment(idx));
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aml_append(method, while_ctx);
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aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
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aml_append(scope, method);
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aml_append(table, scope);
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}
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static Aml *build_osc_method(void)
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{
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Aml *if_ctx;
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Aml *if_ctx2;
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Aml *else_ctx;
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Aml *method;
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Aml *a_cwd1 = aml_name("CDW1");
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Aml *a_ctrl = aml_local(0);
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method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
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aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
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if_ctx = aml_if(aml_equal(
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aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
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aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
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aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
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aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
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/*
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* Always allow native PME, AER (no dependencies)
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* Allow SHPC (PCI bridges can have SHPC controller)
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*/
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aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
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if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
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/* Unknown revision */
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aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
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aml_append(if_ctx, if_ctx2);
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if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
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/* Capabilities bits were masked */
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aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
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aml_append(if_ctx, if_ctx2);
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/* Update DWORD3 in the buffer */
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aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
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aml_append(method, if_ctx);
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else_ctx = aml_else();
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/* Unrecognized UUID */
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aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
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aml_append(method, else_ctx);
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aml_append(method, aml_return(aml_arg(3)));
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return method;
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}
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static void build_uart_device_aml(Aml *table)
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{
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Aml *dev;
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@ -360,57 +259,37 @@ build_la_ged_aml(Aml *dsdt, MachineState *machine)
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}
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}
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static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
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{
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struct GPEXConfig cfg = {
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.mmio64.base = VIRT_PCI_MEM_BASE,
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.mmio64.size = VIRT_PCI_MEM_SIZE,
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.pio.base = VIRT_PCI_IO_BASE,
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.pio.size = VIRT_PCI_IO_SIZE,
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.ecam.base = VIRT_PCI_CFG_BASE,
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.ecam.size = VIRT_PCI_CFG_SIZE,
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.irq = PCH_PIC_IRQ_OFFSET + VIRT_DEVICE_IRQS,
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.bus = lams->pci_bus,
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};
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acpi_dsdt_add_gpex(scope, &cfg);
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}
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/* build DSDT */
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static void
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build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
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{
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Aml *dsdt, *sb_scope, *scope, *dev, *crs, *pkg;
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int root_bus_limit = 0x7F;
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Aml *dsdt, *scope, *pkg;
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LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
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AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = lams->oem_id,
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.oem_table_id = lams->oem_table_id };
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acpi_table_begin(&table, table_data);
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dsdt = init_aml_allocator();
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build_dbg_aml(dsdt);
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sb_scope = aml_scope("_SB");
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dev = aml_device("PCI0");
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aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
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aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
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aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
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aml_append(dev, aml_name_decl("_UID", aml_int(1)));
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aml_append(dev, build_osc_method());
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aml_append(sb_scope, dev);
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aml_append(dsdt, sb_scope);
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build_gpex_pci0_int(dsdt);
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build_uart_device_aml(dsdt);
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build_pci_device_aml(dsdt, lams);
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build_la_ged_aml(dsdt, machine);
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scope = aml_scope("\\_SB.PCI0");
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/* Build PCI0._CRS */
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crs = aml_resource_template();
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aml_append(crs,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000, 0x0, root_bus_limit,
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0x0000, root_bus_limit + 1));
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aml_append(crs,
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aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
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AML_POS_DECODE, AML_ENTIRE_RANGE,
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0x0000, 0x0000, 0xFFFF, 0x18000000, 0x10000));
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aml_append(crs,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_CACHEABLE, AML_READ_WRITE,
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0, VIRT_PCI_MEM_BASE,
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VIRT_PCI_MEM_BASE + VIRT_PCI_MEM_SIZE - 1,
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0, VIRT_PCI_MEM_BASE));
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aml_append(scope, aml_name_decl("_CRS", crs));
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aml_append(dsdt, scope);
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/* System State Package */
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scope = aml_scope("\\");
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pkg = aml_package(4);
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@ -387,6 +387,7 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
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d = SYS_BUS_DEVICE(gpex_dev);
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sysbus_realize_and_unref(d, &error_fatal);
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pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
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lams->pci_bus = pci_bus;
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/* Map only part size_ecam bytes of ECAM space */
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ecam_alias = g_new0(MemoryRegion, 1);
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@ -50,6 +50,7 @@ struct LoongArchMachineState {
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DeviceState *acpi_ged;
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int fdt_size;
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DeviceState *platform_bus_dev;
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PCIBus *pci_bus;
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};
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#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt")
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