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target-ppc: retain l{w,d}arx loaded value

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We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed.  It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
This commit is contained in:
Nathan Froyd 2009-08-03 08:43:25 -07:00 committed by malc
parent 174c80d516
commit 18b21a2f83
5 changed files with 17 additions and 10 deletions
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4
target-ppc/cpu.h
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@ -561,7 +561,9 @@ struct CPUPPCState {
/* XER */
target_ulong xer;
/* Reservation address */
target_ulong reserve;
target_ulong reserve_addr;
/* Reservation value */
target_ulong reserve_val;
/* Those ones are used in supervisor mode only */
/* machine state register */

2
target-ppc/helper.c
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@ -2805,7 +2805,7 @@ void cpu_ppc_reset (void *opaque)
env->msr |= (1ULL << MSR_SF);
#endif
hreg_compute_hflags(env);
env->reserve = (target_ulong)-1ULL;
env->reserve_addr = (target_ulong)-1ULL;
/* Be sure no exception or interrupt is pending */
env->pending_interrupts = 0;
env->exception_index = POWERPC_EXCP_NONE;

4
target-ppc/machine.c
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@ -20,7 +20,7 @@ void cpu_save(QEMUFile *f, void *opaque)
for (i = 0; i < 8; i++)
qemu_put_be32s(f, &env->crf[i]);
qemu_put_betls(f, &env->xer);
qemu_put_betls(f, &env->reserve);
qemu_put_betls(f, &env->reserve_addr);
qemu_put_betls(f, &env->msr);
for (i = 0; i < 4; i++)
qemu_put_betls(f, &env->tgpr[i]);
@ -107,7 +107,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < 8; i++)
qemu_get_be32s(f, &env->crf[i]);
qemu_get_betls(f, &env->xer);
qemu_get_betls(f, &env->reserve);
qemu_get_betls(f, &env->reserve_addr);
qemu_get_betls(f, &env->msr);
for (i = 0; i < 4; i++)
qemu_get_betls(f, &env->tgpr[i]);

4
target-ppc/op_helper.c
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@ -329,8 +329,8 @@ static void do_dcbz(target_ulong addr, int dcache_line_size)
for (i = 0 ; i < dcache_line_size ; i += 4) {
stl(addr + i , 0);
}
if (env->reserve == addr)
env->reserve = (target_ulong)-1ULL;
if (env->reserve_addr == addr)
env->reserve_addr = (target_ulong)-1ULL;
}
void helper_dcbz(target_ulong addr)

13
target-ppc/translate.c
View File

@ -158,7 +158,8 @@ void ppc_translate_init(void)
offsetof(CPUState, xer), "xer");
cpu_reserve = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, reserve), "reserve");
offsetof(CPUState, reserve_addr),
"reserve_addr");
cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, fpscr), "fpscr");
@ -3006,12 +3007,14 @@ static void gen_isync(DisasContext *ctx)
static void gen_lwarx(DisasContext *ctx)
{
TCGv t0;
TCGv gpr = cpu_gpr[rD(ctx->opcode)];
gen_set_access_type(ctx, ACCESS_RES);
t0 = tcg_temp_local_new();
gen_addr_reg_index(ctx, t0);
gen_check_align(ctx, t0, 0x03);
gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
gen_qemu_ld32u(ctx, gpr, t0);
tcg_gen_mov_tl(cpu_reserve, t0);
tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
tcg_temp_free(t0);
}
@ -3041,12 +3044,14 @@ static void gen_stwcx_(DisasContext *ctx)
static void gen_ldarx(DisasContext *ctx)
{
TCGv t0;
TCGv gpr = cpu_gpr[rD(ctx->opcode)];
gen_set_access_type(ctx, ACCESS_RES);
t0 = tcg_temp_local_new();
gen_addr_reg_index(ctx, t0);
gen_check_align(ctx, t0, 0x07);
gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
gen_qemu_ld64(ctx, gpr, t0);
tcg_gen_mov_tl(cpu_reserve, t0);
tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
tcg_temp_free(t0);
}
@ -8834,7 +8839,7 @@ void cpu_dump_state (CPUState *env, FILE *f,
a = 'E';
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
}
cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve_addr);
for (i = 0; i < 32; i++) {
if ((i & (RFPL - 1)) == 0)
cpu_fprintf(f, "FPR%02d", i);