target/mips: convert to TranslatorOps
Notes: - DISAS_TOO_MANY replaces the former "break" in the translation loop. However, care must be taken not to overwrite a previous condition in is_jmp; that's why in translate_insn we first check is_jmp and return if it's != DISAS_NEXT. - Added an assert in translate_insn, before exiting due to an exception, to make sure that is_jmp is set to DISAS_NORETURN (the exception generation function always sets it.) - Added an assert for the default case in is_jmp's switch. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Emilio G. Cota
Richard Henderson
parent
12be92588c
commit
18f440edfb
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@ -1432,6 +1432,7 @@ static TCGv_i64 msa_wr_d[64];
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typedef struct DisasContext {
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DisasContextBase base;
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target_ulong saved_pc;
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target_ulong page_start;
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uint32_t opcode;
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int insn_flags;
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int32_t CP0_Config1;
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@ -20194,24 +20195,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUMIPSState *env = cs->env_ptr;
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DisasContext ctx1;
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DisasContext *ctx = &ctx1;
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target_ulong page_start;
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int max_insns;
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int insn_bytes;
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int is_slot;
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ctx->base.tb = tb;
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ctx->base.pc_first = tb->pc;
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ctx->base.pc_next = tb->pc;
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ctx->base.is_jmp = DISAS_NEXT;
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ctx->base.singlestep_enabled = cs->singlestep_enabled;
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ctx->base.num_insns = 0;
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page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
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ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
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ctx->saved_pc = -1;
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ctx->insn_flags = env->insn_flags;
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ctx->CP0_Config1 = env->CP0_Config1;
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@ -20244,99 +20233,102 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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#endif
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ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ?
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MO_UNALN : MO_ALIGN;
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max_insns = tb_cflags(tb) & CF_COUNT_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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}
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if (max_insns > TCG_MAX_INSNS) {
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max_insns = TCG_MAX_INSNS;
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LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
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ctx->hflags);
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}
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static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
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{
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}
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static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
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ctx->btarget);
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}
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static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
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const CPUBreakpoint *bp)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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save_cpu_state(ctx, 1);
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ctx->base.is_jmp = DISAS_NORETURN;
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gen_helper_raise_exception_debug(cpu_env);
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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ctx->base.pc_next += 4;
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return true;
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}
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static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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CPUMIPSState *env = cs->env_ptr;
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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int insn_bytes;
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int is_slot;
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is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
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if (!(ctx->hflags & MIPS_HFLAG_M16)) {
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ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
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insn_bytes = 4;
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decode_opc(env, ctx);
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} else if (ctx->insn_flags & ASE_MICROMIPS) {
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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insn_bytes = decode_micromips_opc(env, ctx);
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} else if (ctx->insn_flags & ASE_MIPS16) {
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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insn_bytes = decode_mips16_opc(env, ctx);
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} else {
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generate_exception_end(ctx, EXCP_RI);
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g_assert(ctx->base.is_jmp == DISAS_NORETURN);
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return;
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}
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LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx->mem_idx, ctx->hflags);
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gen_tb_start(tb);
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while (ctx->base.is_jmp == DISAS_NEXT) {
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tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
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ctx->btarget);
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ctx->base.num_insns++;
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if (unlikely(cpu_breakpoint_test(cs, ctx->base.pc_next, BP_ANY))) {
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save_cpu_state(ctx, 1);
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ctx->base.is_jmp = DISAS_NORETURN;
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gen_helper_raise_exception_debug(cpu_env);
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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ctx->base.pc_next += 4;
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goto done_generating;
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
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MIPS_HFLAG_FBNSLOT))) {
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/* force to generate branch as there is neither delay nor
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forbidden slot */
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is_slot = 1;
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}
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if (ctx->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
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gen_io_start();
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if ((ctx->hflags & MIPS_HFLAG_M16) &&
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(ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
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/* Force to generate branch as microMIPS R6 doesn't restrict
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branches in the forbidden slot. */
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is_slot = 1;
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}
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is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
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if (!(ctx->hflags & MIPS_HFLAG_M16)) {
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ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
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insn_bytes = 4;
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decode_opc(env, ctx);
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} else if (ctx->insn_flags & ASE_MICROMIPS) {
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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insn_bytes = decode_micromips_opc(env, ctx);
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} else if (ctx->insn_flags & ASE_MIPS16) {
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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insn_bytes = decode_mips16_opc(env, ctx);
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} else {
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
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MIPS_HFLAG_FBNSLOT))) {
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/* force to generate branch as there is neither delay nor
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forbidden slot */
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is_slot = 1;
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}
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if ((ctx->hflags & MIPS_HFLAG_M16) &&
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(ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
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/* Force to generate branch as microMIPS R6 doesn't restrict
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branches in the forbidden slot. */
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is_slot = 1;
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}
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}
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if (is_slot) {
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gen_branch(ctx, insn_bytes);
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}
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ctx->base.pc_next += insn_bytes;
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/* Execute a branch and its delay slot as a single instruction.
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This is what GDB expects and is consistent with what the
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hardware does (e.g. if a delay slot instruction faults, the
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reported PC is the PC of the branch). */
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if (ctx->base.singlestep_enabled &&
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(ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
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break;
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}
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if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
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break;
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}
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if (tcg_op_buf_full()) {
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break;
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}
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if (ctx->base.num_insns >= max_insns) {
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break;
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}
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if (singlestep)
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break;
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}
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if (tb_cflags(tb) & CF_LAST_IO) {
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gen_io_end();
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if (is_slot) {
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gen_branch(ctx, insn_bytes);
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}
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ctx->base.pc_next += insn_bytes;
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if (ctx->base.is_jmp != DISAS_NEXT) {
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return;
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}
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/* Execute a branch and its delay slot as a single instruction.
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This is what GDB expects and is consistent with what the
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hardware does (e.g. if a delay slot instruction faults, the
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reported PC is the PC of the branch). */
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if (ctx->base.singlestep_enabled &&
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(ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
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ctx->base.is_jmp = DISAS_TOO_MANY;
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}
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if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
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ctx->base.is_jmp = DISAS_TOO_MANY;
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}
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}
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static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
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save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
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gen_helper_raise_exception_debug(cpu_env);
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@ -20347,6 +20339,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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tcg_gen_lookup_and_goto_ptr();
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break;
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case DISAS_NEXT:
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case DISAS_TOO_MANY:
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save_cpu_state(ctx, 0);
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gen_goto_tb(ctx, 0, ctx->base.pc_next);
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break;
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@ -20354,28 +20347,34 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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tcg_gen_exit_tb(0);
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break;
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case DISAS_NORETURN:
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default:
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break;
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default:
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g_assert_not_reached();
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}
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}
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done_generating:
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gen_tb_end(tb, ctx->base.num_insns);
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}
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tb->size = ctx->base.pc_next - ctx->base.pc_first;
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tb->icount = ctx->base.num_insns;
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static void mips_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
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{
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qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
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log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
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}
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#ifdef DEBUG_DISAS
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LOG_DISAS("\n");
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(ctx->base.pc_first)) {
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qemu_log_lock();
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qemu_log("IN: %s\n", lookup_symbol(ctx->base.pc_first));
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log_target_disas(cs, ctx->base.pc_first,
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ctx->base.pc_next - ctx->base.pc_first);
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qemu_log("\n");
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qemu_log_unlock();
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}
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#endif
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static const TranslatorOps mips_tr_ops = {
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.init_disas_context = mips_tr_init_disas_context,
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.tb_start = mips_tr_tb_start,
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.insn_start = mips_tr_insn_start,
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.breakpoint_check = mips_tr_breakpoint_check,
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.translate_insn = mips_tr_translate_insn,
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.tb_stop = mips_tr_tb_stop,
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.disas_log = mips_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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DisasContext ctx;
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translator_loop(&mips_tr_ops, &ctx.base, cs, tb);
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}
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static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
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