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target/mips: Fix TX79 LQ/SQ opcodes

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The base register address offset is *signed*.

Cc: qemu-stable@nongnu.org
Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914090447.12557-1-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-09-14 11:02:41 +02:00
parent 04591b3ddd
commit 18f86aecd6
1 changed files with 1 additions and 1 deletions
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target/mips/tcg/tx79.decode
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@ -24,7 +24,7 @@
@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0
@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0
@ldst ...... base:5 rt:5 offset:16 &i
@ldst ...... base:5 rt:5 offset:s16 &i
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