target-arm: Add trace events for the generic timers
Add some useful trace events for the ARM generic timers (notably the various register writes and the resulting IRQ line state). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1476294876-12340-3-git-send-email-peter.maydell@linaro.org
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@ -155,6 +155,7 @@ trace-events-y += hw/alpha/trace-events
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trace-events-y += ui/trace-events
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trace-events-y += ui/trace-events
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trace-events-y += audio/trace-events
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trace-events-y += audio/trace-events
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trace-events-y += net/trace-events
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trace-events-y += net/trace-events
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trace-events-y += target-arm/trace-events
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trace-events-y += target-i386/trace-events
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trace-events-y += target-i386/trace-events
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trace-events-y += target-sparc/trace-events
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trace-events-y += target-sparc/trace-events
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trace-events-y += target-s390x/trace-events
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trace-events-y += target-s390x/trace-events
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@ -1,4 +1,5 @@
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "trace.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "internals.h"
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#include "internals.h"
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#include "exec/gdbstub.h"
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#include "exec/gdbstub.h"
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@ -1560,10 +1561,13 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
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/* Note that this must be unsigned 64 bit arithmetic: */
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/* Note that this must be unsigned 64 bit arithmetic: */
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int istatus = count - offset >= gt->cval;
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int istatus = count - offset >= gt->cval;
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uint64_t nexttick;
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uint64_t nexttick;
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int irqstate;
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gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
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gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
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qemu_set_irq(cpu->gt_timer_outputs[timeridx],
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(istatus && !(gt->ctl & 2)));
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irqstate = (istatus && !(gt->ctl & 2));
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qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
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if (istatus) {
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if (istatus) {
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/* Next transition is when count rolls back over to zero */
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/* Next transition is when count rolls back over to zero */
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nexttick = UINT64_MAX;
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nexttick = UINT64_MAX;
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@ -1580,11 +1584,13 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
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nexttick = INT64_MAX / GTIMER_SCALE;
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nexttick = INT64_MAX / GTIMER_SCALE;
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}
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}
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timer_mod(cpu->gt_timer[timeridx], nexttick);
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timer_mod(cpu->gt_timer[timeridx], nexttick);
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trace_arm_gt_recalc(timeridx, irqstate, nexttick);
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} else {
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} else {
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/* Timer disabled: ISTATUS and timer output always clear */
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/* Timer disabled: ISTATUS and timer output always clear */
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gt->ctl &= ~4;
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gt->ctl &= ~4;
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qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
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qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
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timer_del(cpu->gt_timer[timeridx]);
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timer_del(cpu->gt_timer[timeridx]);
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trace_arm_gt_recalc_disabled(timeridx);
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}
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}
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}
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}
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@ -1610,6 +1616,7 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
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int timeridx,
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int timeridx,
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uint64_t value)
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uint64_t value)
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{
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{
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trace_arm_gt_cval_write(timeridx, value);
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env->cp15.c14_timer[timeridx].cval = value;
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env->cp15.c14_timer[timeridx].cval = value;
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gt_recalc_timer(arm_env_get_cpu(env), timeridx);
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gt_recalc_timer(arm_env_get_cpu(env), timeridx);
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}
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}
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@ -1629,6 +1636,7 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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{
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uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
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uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
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trace_arm_gt_tval_write(timeridx, value);
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env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
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env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
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sextract64(value, 0, 32);
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sextract64(value, 0, 32);
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gt_recalc_timer(arm_env_get_cpu(env), timeridx);
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gt_recalc_timer(arm_env_get_cpu(env), timeridx);
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@ -1641,6 +1649,7 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
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uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
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trace_arm_gt_ctl_write(timeridx, value);
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env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
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env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
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if ((oldval ^ value) & 1) {
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if ((oldval ^ value) & 1) {
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/* Enable toggled */
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/* Enable toggled */
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@ -1649,8 +1658,10 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
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/* IMASK toggled: don't need to recalculate,
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/* IMASK toggled: don't need to recalculate,
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* just set the interrupt line based on ISTATUS
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* just set the interrupt line based on ISTATUS
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*/
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*/
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qemu_set_irq(cpu->gt_timer_outputs[timeridx],
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int irqstate = (oldval & 4) && !(value & 2);
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(oldval & 4) && !(value & 2));
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trace_arm_gt_imask_toggle(timeridx, irqstate);
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qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
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}
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}
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}
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}
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@ -1715,6 +1726,7 @@ static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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trace_arm_gt_cntvoff_write(value);
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raw_write(env, ri, value);
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raw_write(env, ri, value);
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gt_recalc_timer(cpu, GTIMER_VIRT);
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gt_recalc_timer(cpu, GTIMER_VIRT);
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}
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}
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@ -0,0 +1,10 @@
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# See docs/tracing.txt for syntax documentation.
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# target-arm/helper.c
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arm_gt_recalc(int timer, int irqstate, uint64_t nexttick) "gt recalc: timer %d irqstate %d next tick %" PRIx64
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arm_gt_recalc_disabled(int timer) "gt recalc: timer %d irqstate 0 timer disabled"
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arm_gt_cval_write(int timer, uint64_t value) "gt_cval_write: timer %d value %" PRIx64
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arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value %" PRIx64
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arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value %" PRIx64
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arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK toggle, new irqstate %d"
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arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value %" PRIx64
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