target/arm: Add el_is_in_host
This (newish) ARM pseudocode function is easier to work with than open-coded tests for HCR_E2H etc. Use of the function will be staged into the code base in parts. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -5282,6 +5282,34 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
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return ret;
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return ret;
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}
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}
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/*
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* Corresponds to ARM pseudocode function ELIsInHost().
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*/
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bool el_is_in_host(CPUARMState *env, int el)
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{
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uint64_t mask;
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/*
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* Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
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* Perform the simplest bit tests first, and validate EL2 afterward.
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*/
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if (el & 1) {
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return false; /* EL1 or EL3 */
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}
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/*
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* Note that hcr_write() checks isar_feature_aa64_vh(),
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* aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
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*/
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mask = el ? HCR_E2H : HCR_E2H | HCR_TGE;
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if ((env->cp15.hcr_el2 & mask) != mask) {
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return false;
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}
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/* TGE and/or E2H set: double check those bits are currently legal. */
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return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2);
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}
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static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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uint64_t value)
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{
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{
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@ -1347,6 +1347,8 @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
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void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
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void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
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#endif
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#endif
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bool el_is_in_host(CPUARMState *env, int el);
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void aa32_max_features(ARMCPU *cpu);
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void aa32_max_features(ARMCPU *cpu);
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#endif
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#endif
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