From 1989205c4e973bc7f9fac0ce0700993f30582538 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Jul 2020 18:48:16 +0800 Subject: [PATCH] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20200710104920.13550-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 433cdacbe1..7cd08f0868 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -937,7 +937,7 @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_vec_sub8_i64(d, b, a); + tcg_gen_vec_sub16_i64(d, b, a); } static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)