From 19b82e3e44c8ed7a2e06eb2027f0a2808aa8142b Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Thu, 17 Feb 2022 11:19:21 +0100 Subject: [PATCH] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Passing PIIX4State rather than just the qemu_irq allows for resolving the global piix4_dev variable. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin Message-Id: <20220217101924.15347-5-shentey@gmail.com> Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 179968b18e..caa2002e2c 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -57,7 +57,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - qemu_irq *pic = opaque; + PIIX4State *s = opaque; PCIBus *bus = pci_get_bus(piix4_dev); /* now we change the pic irq level according to the piix irq mappings */ @@ -71,7 +71,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) pic_level |= pci_bus_get_irq_level(bus, i); } } - qemu_set_irq(pic[pic_irq], pic_level); + qemu_set_irq(s->isa[pic_irq], pic_level); } } @@ -319,7 +319,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) NULL, 0, NULL); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->isa, 4); + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4); return dev; }