target/ppc: powerpc_excp: Set alternate SRRs directly
There are currently only two interrupts that use alternate SRRs, so let them write to them directly during the setup code. No functional change intended. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20211229165751.3774248-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
parent
84ade98e87
commit
19e70626f8
|
@ -370,7 +370,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
|
||||||
CPUState *cs = CPU(cpu);
|
CPUState *cs = CPU(cpu);
|
||||||
CPUPPCState *env = &cpu->env;
|
CPUPPCState *env = &cpu->env;
|
||||||
target_ulong msr, new_msr, vector;
|
target_ulong msr, new_msr, vector;
|
||||||
int srr0, srr1, asrr0, asrr1, lev = -1;
|
int srr0, srr1, lev = -1;
|
||||||
|
|
||||||
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
|
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
|
||||||
" => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
|
" => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
|
||||||
|
@ -392,8 +392,6 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
|
||||||
/* target registers */
|
/* target registers */
|
||||||
srr0 = SPR_SRR0;
|
srr0 = SPR_SRR0;
|
||||||
srr1 = SPR_SRR1;
|
srr1 = SPR_SRR1;
|
||||||
asrr0 = -1;
|
|
||||||
asrr1 = -1;
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* check for special resume at 0x100 from doze/nap/sleep/winkle on
|
* check for special resume at 0x100 from doze/nap/sleep/winkle on
|
||||||
|
@ -483,8 +481,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
|
||||||
/* FIXME: choose one or the other based on CPU type */
|
/* FIXME: choose one or the other based on CPU type */
|
||||||
srr0 = SPR_BOOKE_MCSRR0;
|
srr0 = SPR_BOOKE_MCSRR0;
|
||||||
srr1 = SPR_BOOKE_MCSRR1;
|
srr1 = SPR_BOOKE_MCSRR1;
|
||||||
asrr0 = SPR_BOOKE_CSRR0;
|
|
||||||
asrr1 = SPR_BOOKE_CSRR1;
|
env->spr[SPR_BOOKE_CSRR0] = env->nip;
|
||||||
|
env->spr[SPR_BOOKE_CSRR1] = msr;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
|
@ -643,8 +642,10 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
|
||||||
/* FIXME: choose one or the other based on CPU type */
|
/* FIXME: choose one or the other based on CPU type */
|
||||||
srr0 = SPR_BOOKE_DSRR0;
|
srr0 = SPR_BOOKE_DSRR0;
|
||||||
srr1 = SPR_BOOKE_DSRR1;
|
srr1 = SPR_BOOKE_DSRR1;
|
||||||
asrr0 = SPR_BOOKE_CSRR0;
|
|
||||||
asrr1 = SPR_BOOKE_CSRR1;
|
env->spr[SPR_BOOKE_CSRR0] = env->nip;
|
||||||
|
env->spr[SPR_BOOKE_CSRR1] = msr;
|
||||||
|
|
||||||
/* DBSR already modified by caller */
|
/* DBSR already modified by caller */
|
||||||
} else {
|
} else {
|
||||||
cpu_abort(cs, "Debug exception triggered on unsupported model\n");
|
cpu_abort(cs, "Debug exception triggered on unsupported model\n");
|
||||||
|
@ -911,14 +912,6 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
|
||||||
|
|
||||||
vector |= env->excp_prefix;
|
vector |= env->excp_prefix;
|
||||||
|
|
||||||
/* If any alternate SRR register are defined, duplicate saved values */
|
|
||||||
if (asrr0 != -1) {
|
|
||||||
env->spr[asrr0] = env->nip;
|
|
||||||
}
|
|
||||||
if (asrr1 != -1) {
|
|
||||||
env->spr[asrr1] = msr;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(TARGET_PPC64)
|
#if defined(TARGET_PPC64)
|
||||||
if (excp_model == POWERPC_EXCP_BOOKE) {
|
if (excp_model == POWERPC_EXCP_BOOKE) {
|
||||||
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
|
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
|
||||||
|
|
Loading…
Reference in New Issue