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Avoid address_space_rw() with a constant is_write argument

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The address_space_rw() function allows either reads or writes
depending on the is_write argument passed to it; this is useful
when the direction of the access is determined programmatically
(as for instance when handling the KVM_EXIT_MMIO exit reason).
Under the hood it just calls either address_space_write() or
address_space_read_full().

We also use it a lot with a constant is_write argument, though,
which has two issues:
 * when reading "address_space_rw(..., 1)" this is less
   immediately clear to the reader as being a write than
   "address_space_write(...)"
 * calling address_space_rw() bypasses the optimization
   in address_space_read() that fast-paths reads of a
   fixed length

This commit was produced with the included Coccinelle script
scripts/coccinelle/exec_rw_const.cocci.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20200218112457.22712-1-peter.maydell@linaro.org>
[PMD: Update macvm_set_cr0() reported by Laurent Vivier]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
Peter Maydell 2020-02-18 11:24:57 +00:00 committed by Philippe Mathieu-Daudé
parent 1ccda935d4
commit 19f7034773
13 changed files with 119 additions and 107 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
accel/kvm/kvm-all.c
View File

@ -2178,9 +2178,9 @@ void kvm_flush_coalesced_mmio_buffer(void)
ent = &ring->coalesced_mmio[ring->first]; ent = &ring->coalesced_mmio[ring->first];
if (ent->pio == 1) { if (ent->pio == 1) {
address_space_rw(&address_space_io, ent->phys_addr, address_space_write(&address_space_io, ent->phys_addr,
MEMTXATTRS_UNSPECIFIED, ent->data, MEMTXATTRS_UNSPECIFIED, ent->data,
ent->len, true); ent->len);
} else { } else {
cpu_physical_memory_write(ent->phys_addr, ent->data, ent->len); cpu_physical_memory_write(ent->phys_addr, ent->data, ent->len);
} }

4
dma-helpers.c
View File

@ -28,8 +28,8 @@ int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
memset(fillbuf, c, FILLBUF_SIZE); memset(fillbuf, c, FILLBUF_SIZE);
while (len > 0) { while (len > 0) {
l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, error |= address_space_write(as, addr, MEMTXATTRS_UNSPECIFIED,
fillbuf, l, true); fillbuf, l);
len -= l; len -= l;
addr += l; addr += l;
} }

4
exec.c
View File

@ -3815,8 +3815,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,
attrs, buf, l); attrs, buf, l);
} else { } else {
address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, attrs, buf, address_space_read(cpu->cpu_ases[asidx].as, phys_addr, attrs, buf,
l, false); l);
} }
len -= l; len -= l;
buf += l; buf += l;

11
hw/dma/xlnx-zdma.c
View File

@ -311,8 +311,7 @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
return false; return false;
} }
address_space_rw(s->dma_as, addr, s->attr, address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr));
buf, sizeof(XlnxZDMADescr), false);
return true; return true;
} }
@ -364,7 +363,7 @@ static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type,
} else { } else {
addr = zdma_get_regaddr64(s, basereg); addr = zdma_get_regaddr64(s, basereg);
addr += sizeof(s->dsc_dst); addr += sizeof(s->dsc_dst);
address_space_rw(s->dma_as, addr, s->attr, &next, 8, false); address_space_read(s->dma_as, addr, s->attr, &next, 8);
zdma_put_regaddr64(s, basereg, next); zdma_put_regaddr64(s, basereg, next);
} }
return next; return next;
@ -416,8 +415,7 @@ static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
} }
} }
address_space_rw(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen, address_space_write(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen);
true);
if (burst_type == AXI_BURST_INCR) { if (burst_type == AXI_BURST_INCR) {
s->dsc_dst.addr += dlen; s->dsc_dst.addr += dlen;
} }
@ -493,8 +491,7 @@ static void zdma_process_descr(XlnxZDMA *s)
len = s->cfg.bus_width / 8; len = s->cfg.bus_width / 8;
} }
} else { } else {
address_space_rw(s->dma_as, src_addr, s->attr, s->buf, len, address_space_read(s->dma_as, src_addr, s->attr, s->buf, len);
false);
if (burst_type == AXI_BURST_INCR) { if (burst_type == AXI_BURST_INCR) {
src_addr += len; src_addr += len;
} }

70
hw/net/dp8393x.c
View File

@ -275,8 +275,8 @@ static void dp8393x_do_load_cam(dp8393xState *s)
while (s->regs[SONIC_CDC] & 0x1f) { while (s->regs[SONIC_CDC] & 0x1f) {
/* Fill current entry */ /* Fill current entry */
address_space_rw(&s->as, dp8393x_cdp(s), address_space_read(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, false); MEMTXATTRS_UNSPECIFIED, s->data, size);
s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
@ -293,8 +293,8 @@ static void dp8393x_do_load_cam(dp8393xState *s)
} }
/* Read CAM enable */ /* Read CAM enable */
address_space_rw(&s->as, dp8393x_cdp(s), address_space_read(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, false); MEMTXATTRS_UNSPECIFIED, s->data, size);
s->regs[SONIC_CE] = dp8393x_get(s, width, 0); s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
@ -311,8 +311,8 @@ static void dp8393x_do_read_rra(dp8393xState *s)
/* Read memory */ /* Read memory */
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width; size = sizeof(uint16_t) * 4 * width;
address_space_rw(&s->as, dp8393x_rrp(s), address_space_read(&s->as, dp8393x_rrp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, false); MEMTXATTRS_UNSPECIFIED, s->data, size);
/* Update SONIC registers */ /* Update SONIC registers */
s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
@ -426,8 +426,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * 6 * width; size = sizeof(uint16_t) * 6 * width;
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
MEMTXATTRS_UNSPECIFIED, s->data, size, false); MEMTXATTRS_UNSPECIFIED, s->data, size);
tx_len = 0; tx_len = 0;
/* Update registers */ /* Update registers */
@ -451,18 +451,19 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
if (tx_len + len > sizeof(s->tx_buffer)) { if (tx_len + len > sizeof(s->tx_buffer)) {
len = sizeof(s->tx_buffer) - tx_len; len = sizeof(s->tx_buffer) - tx_len;
} }
address_space_rw(&s->as, dp8393x_tsa(s), address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED,
MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len);
&s->tx_buffer[tx_len], len, false);
tx_len += len; tx_len += len;
i++; i++;
if (i != s->regs[SONIC_TFC]) { if (i != s->regs[SONIC_TFC]) {
/* Read next fragment details */ /* Read next fragment details */
size = sizeof(uint16_t) * 3 * width; size = sizeof(uint16_t) * 3 * width;
address_space_rw(&s->as, address_space_read(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width, dp8393x_ttda(s)
MEMTXATTRS_UNSPECIFIED, s->data, size, false); + sizeof(uint16_t) * width * (4 + 3 * i),
MEMTXATTRS_UNSPECIFIED, s->data,
size);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
@ -495,18 +496,18 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
dp8393x_put(s, width, 0, dp8393x_put(s, width, 0,
s->regs[SONIC_TCR] & 0x0fff); /* status */ s->regs[SONIC_TCR] & 0x0fff); /* status */
size = sizeof(uint16_t) * width; size = sizeof(uint16_t) * width;
address_space_rw(&s->as, address_space_write(&s->as, dp8393x_ttda(s),
dp8393x_ttda(s), MEMTXATTRS_UNSPECIFIED, s->data, size);
MEMTXATTRS_UNSPECIFIED, s->data, size, true);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */ /* Read footer of packet */
size = sizeof(uint16_t) * width; size = sizeof(uint16_t) * width;
address_space_rw(&s->as, address_space_read(&s->as,
dp8393x_ttda(s) + dp8393x_ttda(s)
sizeof(uint16_t) * + sizeof(uint16_t) * width
(4 + 3 * s->regs[SONIC_TFC]) * width, * (4 + 3 * s->regs[SONIC_TFC]),
MEMTXATTRS_UNSPECIFIED, s->data, size, false); MEMTXATTRS_UNSPECIFIED, s->data,
size);
s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1;
if (dp8393x_get(s, width, 0) & 0x1) { if (dp8393x_get(s, width, 0) & 0x1) {
/* EOL detected */ /* EOL detected */
@ -768,8 +769,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Are we still in resource exhaustion? */ /* Are we still in resource exhaustion? */
size = sizeof(uint16_t) * 1 * width; size = sizeof(uint16_t) * 1 * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
s->data, size, false); s->data, size);
if (dp8393x_get(s, width, 0) & 0x1) { if (dp8393x_get(s, width, 0) & 0x1) {
/* Still EOL ; stop reception */ /* Still EOL ; stop reception */
return -1; return -1;
@ -788,10 +789,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Put packet into RBA */ /* Put packet into RBA */
DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
address = dp8393x_crba(s); address = dp8393x_crba(s);
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, rx_len); address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
buf, rx_len);
address += rx_len; address += rx_len;
address_space_rw(&s->as, address, address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
MEMTXATTRS_UNSPECIFIED, &checksum, 4, true); &checksum, 4);
rx_len += 4; rx_len += 4;
s->regs[SONIC_CRBA1] = address >> 16; s->regs[SONIC_CRBA1] = address >> 16;
s->regs[SONIC_CRBA0] = address & 0xffff; s->regs[SONIC_CRBA0] = address & 0xffff;
@ -819,13 +821,15 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
size = sizeof(uint16_t) * 5 * width; size = sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, dp8393x_crda(s), address_space_write(&s->as, dp8393x_crda(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, true); MEMTXATTRS_UNSPECIFIED,
s->data, size);
/* Move to next descriptor */ /* Move to next descriptor */
size = sizeof(uint16_t) * width; size = sizeof(uint16_t) * width;
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, address_space_read(&s->as,
MEMTXATTRS_UNSPECIFIED, s->data, size, false); dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
MEMTXATTRS_UNSPECIFIED, s->data, size);
s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
if (s->regs[SONIC_LLFA] & 0x1) { if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */ /* EOL detected */
@ -838,8 +842,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
offset += sizeof(uint16_t); offset += sizeof(uint16_t);
} }
s->data[0] = 0; s->data[0] = 0;
address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED, address_space_write(&s->as, offset, MEMTXATTRS_UNSPECIFIED,
s->data, sizeof(uint16_t), true); s->data, sizeof(uint16_t));
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);

22
hw/net/i82596.c
View File

@ -148,8 +148,8 @@ static void i82596_transmit(I82596State *s, uint32_t addr)
if (s->nic && len) { if (s->nic && len) {
assert(len <= sizeof(s->tx_buffer)); assert(len <= sizeof(s->tx_buffer));
address_space_rw(&address_space_memory, tba, address_space_read(&address_space_memory, tba,
MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len, false); MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len);
DBG(PRINT_PKTHDR("Send", &s->tx_buffer)); DBG(PRINT_PKTHDR("Send", &s->tx_buffer));
DBG(printf("Sending %d bytes\n", len)); DBG(printf("Sending %d bytes\n", len));
qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len); qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len);
@ -172,8 +172,8 @@ static void set_individual_address(I82596State *s, uint32_t addr)
nc = qemu_get_queue(s->nic); nc = qemu_get_queue(s->nic);
m = s->conf.macaddr.a; m = s->conf.macaddr.a;
address_space_rw(&address_space_memory, addr + 8, address_space_read(&address_space_memory, addr + 8,
MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN, false); MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN);
qemu_format_nic_info_str(nc, m); qemu_format_nic_info_str(nc, m);
trace_i82596_new_mac(nc->info_str); trace_i82596_new_mac(nc->info_str);
} }
@ -190,9 +190,8 @@ static void set_multicast_list(I82596State *s, uint32_t addr)
} }
for (i = 0; i < mc_count; i++) { for (i = 0; i < mc_count; i++) {
uint8_t multicast_addr[ETH_ALEN]; uint8_t multicast_addr[ETH_ALEN];
address_space_rw(&address_space_memory, address_space_read(&address_space_memory, addr + i * ETH_ALEN,
addr + i * ETH_ALEN, MEMTXATTRS_UNSPECIFIED, MEMTXATTRS_UNSPECIFIED, multicast_addr, ETH_ALEN);
multicast_addr, ETH_ALEN, false);
DBG(printf("Add multicast entry " MAC_FMT "\n", DBG(printf("Add multicast entry " MAC_FMT "\n",
MAC_ARG(multicast_addr))); MAC_ARG(multicast_addr)));
unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) & unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) &
@ -260,9 +259,8 @@ static void command_loop(I82596State *s)
byte_cnt = MAX(byte_cnt, 4); byte_cnt = MAX(byte_cnt, 4);
byte_cnt = MIN(byte_cnt, sizeof(s->config)); byte_cnt = MIN(byte_cnt, sizeof(s->config));
/* copy byte_cnt max. */ /* copy byte_cnt max. */
address_space_rw(&address_space_memory, s->cmd_p + 8, address_space_read(&address_space_memory, s->cmd_p + 8,
MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt, MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt);
false);
/* config byte according to page 35ff */ /* config byte according to page 35ff */
s->config[2] &= 0x82; /* mask valid bits */ s->config[2] &= 0x82; /* mask valid bits */
s->config[2] |= 0x40; s->config[2] |= 0x40;
@ -647,8 +645,8 @@ ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz)
buf += num; buf += num;
len -= num; len -= num;
if (len == 0) { /* copy crc */ if (len == 0) { /* copy crc */
address_space_rw(&address_space_memory, rba - 4, address_space_write(&address_space_memory, rba - 4,
MEMTXATTRS_UNSPECIFIED, crc_ptr, 4, true); MEMTXATTRS_UNSPECIFIED, crc_ptr, 4);
} }
num |= 0x4000; /* set F BIT */ num |= 0x4000; /* set F BIT */

5
hw/net/lasi_i82596.c
View File

@ -55,8 +55,9 @@ static void lasi_82596_mem_write(void *opaque, hwaddr addr,
* Provided for SeaBIOS only. Write MAC of Network card to addr @val. * Provided for SeaBIOS only. Write MAC of Network card to addr @val.
* Needed for the PDC_LAN_STATION_ID_READ PDC call. * Needed for the PDC_LAN_STATION_ID_READ PDC call.
*/ */
address_space_rw(&address_space_memory, val, MEMTXATTRS_UNSPECIFIED, address_space_write(&address_space_memory, val,
d->state.conf.macaddr.a, ETH_ALEN, true); MEMTXATTRS_UNSPECIFIED, d->state.conf.macaddr.a,
ETH_ALEN);
break; break;
} }
} }

8
hw/ppc/pnv_lpc.c
View File

@ -238,16 +238,16 @@ static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
int sz) int sz)
{ {
/* XXX Handle access size limits and FW read caching here */ /* XXX Handle access size limits and FW read caching here */
return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
data, sz, false); data, sz);
} }
static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
int sz) int sz)
{ {
/* XXX Handle access size limits here */ /* XXX Handle access size limits here */
return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
data, sz, true); data, sz);
} }
#define ECCB_CTL_READ PPC_BIT(15) #define ECCB_CTL_READ PPC_BIT(15)

12
hw/s390x/css.c
View File

@ -874,18 +874,18 @@ static inline int ida_read_next_idaw(CcwDataStream *cds)
if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
return -EINVAL; /* channel program check */ return -EINVAL; /* channel program check */
} }
ret = address_space_rw(&address_space_memory, idaw_addr, ret = address_space_read(&address_space_memory, idaw_addr,
MEMTXATTRS_UNSPECIFIED, &idaw.fmt2, MEMTXATTRS_UNSPECIFIED, &idaw.fmt2,
sizeof(idaw.fmt2), false); sizeof(idaw.fmt2));
cds->cda = be64_to_cpu(idaw.fmt2); cds->cda = be64_to_cpu(idaw.fmt2);
} else { } else {
idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw; idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw;
if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
return -EINVAL; /* channel program check */ return -EINVAL; /* channel program check */
} }
ret = address_space_rw(&address_space_memory, idaw_addr, ret = address_space_read(&address_space_memory, idaw_addr,
MEMTXATTRS_UNSPECIFIED, &idaw.fmt1, MEMTXATTRS_UNSPECIFIED, &idaw.fmt1,
sizeof(idaw.fmt1), false); sizeof(idaw.fmt1));
cds->cda = be64_to_cpu(idaw.fmt1); cds->cda = be64_to_cpu(idaw.fmt1);
if (cds->cda & 0x80000000) { if (cds->cda & 0x80000000) {
return -EINVAL; /* channel program check */ return -EINVAL; /* channel program check */

52
qtest.c
View File

@ -429,23 +429,23 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (words[0][5] == 'b') { if (words[0][5] == 'b') {
uint8_t data = value; uint8_t data = value;
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
&data, 1, true); &data, 1);
} else if (words[0][5] == 'w') { } else if (words[0][5] == 'w') {
uint16_t data = value; uint16_t data = value;
tswap16s(&data); tswap16s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
&data, 2, true); &data, 2);
} else if (words[0][5] == 'l') { } else if (words[0][5] == 'l') {
uint32_t data = value; uint32_t data = value;
tswap32s(&data); tswap32s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
&data, 4, true); &data, 4);
} else if (words[0][5] == 'q') { } else if (words[0][5] == 'q') {
uint64_t data = value; uint64_t data = value;
tswap64s(&data); tswap64s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
&data, 8, true); &data, 8);
} }
qtest_send_prefix(chr); qtest_send_prefix(chr);
qtest_send(chr, "OK\n"); qtest_send(chr, "OK\n");
@ -463,22 +463,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (words[0][4] == 'b') { if (words[0][4] == 'b') {
uint8_t data; uint8_t data;
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
&data, 1, false); &data, 1);
value = data; value = data;
} else if (words[0][4] == 'w') { } else if (words[0][4] == 'w') {
uint16_t data; uint16_t data;
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
&data, 2, false); &data, 2);
value = tswap16(data); value = tswap16(data);
} else if (words[0][4] == 'l') { } else if (words[0][4] == 'l') {
uint32_t data; uint32_t data;
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
&data, 4, false); &data, 4);
value = tswap32(data); value = tswap32(data);
} else if (words[0][4] == 'q') { } else if (words[0][4] == 'q') {
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
&value, 8, false); &value, 8);
tswap64s(&value); tswap64s(&value);
} }
qtest_send_prefix(chr); qtest_send_prefix(chr);
@ -498,8 +498,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
g_assert(len); g_assert(len);
data = g_malloc(len); data = g_malloc(len);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
data, len, false); len);
enc = g_malloc(2 * len + 1); enc = g_malloc(2 * len + 1);
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
@ -524,8 +524,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
g_assert(ret == 0); g_assert(ret == 0);
data = g_malloc(len); data = g_malloc(len);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
data, len, false); len);
b64_data = g_base64_encode(data, len); b64_data = g_base64_encode(data, len);
qtest_send_prefix(chr); qtest_send_prefix(chr);
qtest_sendf(chr, "OK %s\n", b64_data); qtest_sendf(chr, "OK %s\n", b64_data);
@ -559,8 +559,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
data[i] = 0; data[i] = 0;
} }
} }
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
data, len, true); len);
g_free(data); g_free(data);
qtest_send_prefix(chr); qtest_send_prefix(chr);
@ -582,8 +582,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (len) { if (len) {
data = g_malloc(len); data = g_malloc(len);
memset(data, pattern, len); memset(data, pattern, len);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
data, len, true); data, len);
g_free(data); g_free(data);
} }
@ -616,8 +616,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
out_len = MIN(out_len, len); out_len = MIN(out_len, len);
} }
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
data, len, true); len);
qtest_send_prefix(chr); qtest_send_prefix(chr);
qtest_send(chr, "OK\n"); qtest_send(chr, "OK\n");

13
scripts/coccinelle/exec_rw_const.cocci
View File

@ -35,6 +35,19 @@ expression E1, E2, E3, E4;
+ address_space_write(E1, E2, E3, V, E4) + address_space_write(E1, E2, E3, V, E4)
) )
// Avoid uses of address_space_rw() with a constant is_write argument.
@@
expression E1, E2, E3, E4, E5;
symbol true, false;
@@
(
- address_space_rw(E1, E2, E3, E4, E5, false)
+ address_space_read(E1, E2, E3, E4, E5)
|
- address_space_rw(E1, E2, E3, E4, E5, true)
+ address_space_write(E1, E2, E3, E4, E5)
)
// Remove useless cast // Remove useless cast
@@ @@
expression E1, E2, E3, E4, E5, E6; expression E1, E2, E3, E4, E5, E6;

7
target/i386/hvf/vmx.h
View File

@ -125,10 +125,9 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) &&
!(efer & MSR_EFER_LME)) { !(efer & MSR_EFER_LME)) {
address_space_rw(&address_space_memory, address_space_read(&address_space_memory,
rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
MEMTXATTRS_UNSPECIFIED, MEMTXATTRS_UNSPECIFIED, pdpte, 32);
pdpte, 32, false);
/* Only set PDPTE when appropriate. */ /* Only set PDPTE when appropriate. */
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]); wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);

12
target/i386/hvf/x86_mmu.c
View File

@ -88,8 +88,8 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
} }
index = gpt_entry(pt->gva, level, pae); index = gpt_entry(pt->gva, level, pae);
address_space_rw(&address_space_memory, gpa + index * pte_size(pae), address_space_read(&address_space_memory, gpa + index * pte_size(pae),
MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae), false); MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae));
pt->pte[level - 1] = pte; pt->pte[level - 1] = pte;
@ -238,8 +238,8 @@ void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes
if (!mmu_gva_to_gpa(cpu, gva, &gpa)) { if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva); VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva);
} else { } else {
address_space_rw(&address_space_memory, gpa, address_space_write(&address_space_memory, gpa,
MEMTXATTRS_UNSPECIFIED, data, copy, true); MEMTXATTRS_UNSPECIFIED, data, copy);
} }
bytes -= copy; bytes -= copy;
@ -259,8 +259,8 @@ void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes)
if (!mmu_gva_to_gpa(cpu, gva, &gpa)) { if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva); VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva);
} }
address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, address_space_read(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED,
data, copy, false); data, copy);
bytes -= copy; bytes -= copy;
gva += copy; gva += copy;