OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

omap_spi: convert to memory API

Browse Source 
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Benoît Canet 2011-11-28 13:53:35 +01:00 committed by Avi Kivity
parent ba1580299d
commit 1a0726900e
1 changed files with 20 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
hw/omap_spi.c
View File

@ -24,6 +24,7 @@
/* Multichannel SPI */
struct omap_mcspi_s {
MemoryRegion iomem;
qemu_irq irq;
int chnum;
@ -129,12 +130,17 @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
omap_mcspi_interrupt_update(s);
}
static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
int ch = 0;
uint32_t ret;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* MCSPI_REVISION */
return 0x91;
@ -199,11 +205,15 @@ static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
int ch = 0;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* MCSPI_REVISION */
case 0x14: /* MCSPI_SYSSTATUS */
@ -267,7 +277,7 @@ static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
if (((value >> 12) & 3) == 3) /* TRM */
fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
if (((value >> 7) & 0x1f) < 3) /* WL */
fprintf(stderr, "%s: invalid WL value (%i)\n",
fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
__FUNCTION__, (value >> 7) & 0x1f);
s->ch[ch].config = value & 0x7fffff;
break;
@ -298,22 +308,15 @@ static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_mcspi_read,
};
static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_mcspi_write,
static const MemoryRegionOps omap_mcspi_ops = {
.read = omap_mcspi_read,
.write = omap_mcspi_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
int iomemtype;
struct omap_mcspi_s *s = (struct omap_mcspi_s *)
g_malloc0(sizeof(struct omap_mcspi_s));
struct omap_mcspi_ch_s *ch = s->ch;
@ -327,9 +330,9 @@ struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
}
omap_mcspi_reset(s);
iomemtype = cpu_register_io_memory(omap_mcspi_readfn,
omap_mcspi_writefn, s, DEVICE_NATIVE_ENDIAN);
omap_l4_attach(ta, 0, iomemtype);
memory_region_init_io(&s->iomem, &omap_mcspi_ops, s, "omap.mcspi",
omap_l4_region_size(ta, 0));
omap_l4_attach_region(ta, 0, &s->iomem);
return s;
}