tcg: Adjust tb_target_set_jmp_target for split-wx
Pass both rx and rw addresses to tb_target_set_jmp_target. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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755bf9e514
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1acbad0f27
@ -382,7 +382,9 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)
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if (TCG_TARGET_HAS_direct_jump) {
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uintptr_t offset = tb->jmp_target_arg[n];
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uintptr_t tc_ptr = (uintptr_t)tb->tc.ptr;
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tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr);
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uintptr_t jmp_rx = tc_ptr + offset;
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uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff;
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tb_target_set_jmp_target(tc_ptr, jmp_rx, jmp_rw, addr);
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} else {
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tb->jmp_target_arg[n] = addr;
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}
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@ -1340,21 +1340,21 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
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}
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}
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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uintptr_t addr)
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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tcg_insn_unit i1, i2;
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TCGType rt = TCG_TYPE_I64;
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TCGReg rd = TCG_REG_TMP;
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uint64_t pair;
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ptrdiff_t offset = addr - jmp_addr;
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ptrdiff_t offset = addr - jmp_rx;
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if (offset == sextract64(offset, 0, 26)) {
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i1 = I3206_B | ((offset >> 2) & 0x3ffffff);
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i2 = NOP;
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} else {
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offset = (addr >> 12) - (jmp_addr >> 12);
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offset = (addr >> 12) - (jmp_rx >> 12);
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/* patch ADRP */
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i1 = I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5 - 2) | rd;
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@ -1362,8 +1362,8 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd;
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}
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pair = (uint64_t)i2 << 32 | i1;
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qatomic_set((uint64_t *)jmp_addr, pair);
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flush_idcache_range(jmp_addr, jmp_addr, 8);
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qatomic_set((uint64_t *)jmp_rw, pair);
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flush_idcache_range(jmp_rx, jmp_rw, 8);
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}
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static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l)
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@ -149,7 +149,7 @@ typedef enum {
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#ifdef CONFIG_SOFTMMU
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#define TCG_TARGET_NEED_LDST_LABELS
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@ -136,7 +136,7 @@ enum {
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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/* not defined -- call should be eliminated at compile time */
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#ifdef CONFIG_SOFTMMU
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#define TCG_TARGET_NEED_LDST_LABELS
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@ -210,11 +210,11 @@ extern bool have_movbe;
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#define TCG_TARGET_extract_i64_valid(ofs, len) \
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(((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32)
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
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uintptr_t jmp_addr, uintptr_t addr)
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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/* patch the branch destination */
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qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
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qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4));
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/* no need to flush icache explicitly */
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}
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@ -2657,11 +2657,11 @@ static void tcg_target_init(TCGContext *s)
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
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}
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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uintptr_t addr)
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2));
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flush_idcache_range(jmp_addr, jmp_addr, 4);
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qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2));
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flush_idcache_range(jmp_rx, jmp_rw, 4);
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}
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typedef struct {
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@ -202,7 +202,7 @@ extern bool use_mips32r2_instructions;
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#ifdef CONFIG_SOFTMMU
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#define TCG_TARGET_NEED_LDST_LABELS
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@ -1722,13 +1722,13 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
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tcg_out32(s, insn);
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}
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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uintptr_t addr)
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_insn_unit i1, i2;
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intptr_t tb_diff = addr - tc_ptr;
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intptr_t br_diff = addr - (jmp_addr + 4);
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intptr_t br_diff = addr - (jmp_rx + 4);
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uint64_t pair;
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/* This does not exercise the range of the branch, but we do
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@ -1752,13 +1752,13 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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/* As per the enclosing if, this is ppc64. Avoid the _Static_assert
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within qatomic_set that would fail to build a ppc32 host. */
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qatomic_set__nocheck((uint64_t *)jmp_addr, pair);
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flush_idcache_range(jmp_addr, jmp_addr, 8);
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qatomic_set__nocheck((uint64_t *)jmp_rw, pair);
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flush_idcache_range(jmp_rx, jmp_rw, 8);
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} else {
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intptr_t diff = addr - jmp_addr;
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intptr_t diff = addr - jmp_rx;
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tcg_debug_assert(in_range_b(diff));
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qatomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
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flush_idcache_range(jmp_addr, jmp_addr, 4);
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qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc));
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flush_idcache_range(jmp_rx, jmp_rw, 4);
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}
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}
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@ -176,7 +176,7 @@ extern bool have_vsx;
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#define TCG_TARGET_HAS_bitsel_vec have_vsx
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#define TCG_TARGET_HAS_cmpsel_vec 0
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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@ -161,7 +161,7 @@ typedef enum {
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#endif
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/* not defined -- call should be eliminated at compile time */
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#define TCG_TARGET_DEFAULT_MO (0)
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@ -146,12 +146,12 @@ enum {
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TCG_AREG0 = TCG_REG_R10,
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};
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
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uintptr_t jmp_addr, uintptr_t addr)
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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/* patch the branch destination */
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intptr_t disp = addr - (jmp_addr - 2);
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qatomic_set((int32_t *)jmp_addr, disp / 2);
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intptr_t disp = addr - (jmp_rx - 2);
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qatomic_set((int32_t *)jmp_rw, disp / 2);
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/* no need to flush icache explicitly */
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}
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@ -1821,11 +1821,11 @@ void tcg_register_jit(const void *buf, size_t buf_size)
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tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
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}
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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uintptr_t addr)
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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intptr_t tb_disp = addr - tc_ptr;
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intptr_t br_disp = addr - jmp_addr;
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intptr_t br_disp = addr - jmp_rx;
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tcg_insn_unit i1, i2;
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/* We can reach the entire address space for ILP32.
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@ -1834,9 +1834,9 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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tcg_debug_assert(br_disp == (int32_t)br_disp);
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if (!USE_REG_TB) {
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qatomic_set((uint32_t *)jmp_addr,
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qatomic_set((uint32_t *)jmp_rw,
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deposit32(CALL, 0, 30, br_disp >> 2));
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flush_idcache_range(jmp_addr, jmp_addr, 4);
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flush_idcache_range(jmp_rx, jmp_rw, 4);
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return;
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}
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@ -1859,6 +1859,6 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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| INSN_IMM13((tb_disp & 0x3ff) | -0x400));
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}
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qatomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1));
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flush_idcache_range(jmp_addr, jmp_addr, 8);
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qatomic_set((uint64_t *)jmp_rw, deposit64(i2, 32, 32, i1));
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flush_idcache_range(jmp_rx, jmp_rw, 8);
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}
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@ -169,7 +169,7 @@ extern bool use_vis3_instructions;
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#define TCG_TARGET_NEED_POOL_LABELS
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@ -199,11 +199,11 @@ void tci_disas(uint8_t opc);
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
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uintptr_t jmp_addr, uintptr_t addr)
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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/* patch the branch destination */
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qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
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qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4));
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/* no need to flush icache explicitly */
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}
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