e2k: disable probe page cache by default
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376350c626
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1ae8e5f53a
@ -130,7 +130,9 @@ void cpu_loop(CPUE2KState *env)
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}
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if (ret == 0) {
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e2k_clear_probe_page_cache(num);
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if (env->enable_pagecache) {
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e2k_clear_probe_page_cache(num);
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}
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ret = do_syscall(env, num, args[1], args[2], args[3],
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args[4], args[5], args[6], args[7], args[8]);
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}
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@ -262,6 +262,7 @@ static struct TCGCPUOps e2k_tcg_ops = {
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static Property e2k_cpu_properties[] = {
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DEFINE_PROP_BOOL("force_save_alc_dst", E2KCPU, env.force_save_alc_dst, false),
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DEFINE_PROP_BOOL("tags", E2KCPU, env.enable_tags, false),
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DEFINE_PROP_BOOL("pagecache", E2KCPU, env.enable_pagecache, false),
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DEFINE_PROP_END_OF_LIST()
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};
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@ -936,6 +936,9 @@ typedef struct CPUArchState {
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/* Enable tags handling.
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* Default: false */
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bool enable_tags;
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/* Enable page cache for speculative memory accesses.
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* Default: false */
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bool enable_pagecache;
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struct e2k_def_t def;
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@ -20,15 +20,20 @@
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static bool e2k_probe_access_cached(CPUE2KState *env, target_ulong page, int flags)
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{
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int index = (page >> TARGET_PAGE_BITS) & (TARGET_PROBE_CACHE_SIZE - 1);
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uint8_t page_flags;
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if (env->probe_cache_page[index] == page) {
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if (env->enable_pagecache && env->probe_cache_page[index] == page) {
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return (env->probe_cache_flags[index] & flags) == flags;
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}
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env->probe_cache_page[index] = page;
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env->probe_cache_flags[index] = page_get_flags(page);
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page_flags = page_get_flags(page);
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return (env->probe_cache_flags[index] & flags) == flags;
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if (env->enable_pagecache) {
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env->probe_cache_page[index] = page;
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env->probe_cache_flags[index] = page_flags;
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}
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return (page_flags & flags) == flags;
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}
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static bool e2k_probe_access(CPUE2KState *env, target_ulong addr, int size, int flags)
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