target-arm: A64: Handle blr lr
For linked branches, updates to the link register happen conceptually after the read of the branch target register. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Cc: qemu-stable@nongnu.org Message-id: 1398926097-28097-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1509,8 +1509,10 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
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switch (opc) {
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case 0: /* BR */
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case 2: /* RET */
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tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
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break;
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case 1: /* BLR */
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tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
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tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
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break;
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case 4: /* ERET */
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@ -1529,7 +1531,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
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return;
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}
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tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
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s->is_jmp = DISAS_JUMP;
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}
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