hardfloat: implement float32/64 addition and subtraction
Performance results (single and double precision) for fp-bench:
1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
add-single: 135.07 MFlops
add-double: 131.60 MFlops
sub-single: 130.04 MFlops
sub-double: 133.01 MFlops
- after:
add-single: 443.04 MFlops
add-double: 301.95 MFlops
sub-single: 411.36 MFlops
sub-double: 293.15 MFlops
2. ARM Aarch64 A57 @ 2.4GHz
- before:
add-single: 44.79 MFlops
add-double: 49.20 MFlops
sub-single: 44.55 MFlops
sub-double: 49.06 MFlops
- after:
add-single: 93.28 MFlops
add-double: 88.27 MFlops
sub-single: 91.47 MFlops
sub-double: 88.27 MFlops
3. IBM POWER8E @ 2.1 GHz
- before:
add-single: 72.59 MFlops
add-double: 72.27 MFlops
sub-single: 75.33 MFlops
sub-double: 70.54 MFlops
- after:
add-single: 112.95 MFlops
add-double: 201.11 MFlops
sub-single: 116.80 MFlops
sub-double: 188.72 MFlops
Note that the IBM and ARM machines benefit from having
HARDFLOAT_2F{32,64}_USE_FP set to 0. Otherwise their performance
can suffer significantly:
- IBM Power8:
add-single: [1] 54.94 vs [0] 116.37 MFlops
add-double: [1] 58.92 vs [0] 201.44 MFlops
- Aarch64 A57:
add-single: [1] 80.72 vs [0] 93.24 MFlops
add-double: [1] 82.10 vs [0] 88.18 MFlops
On the Intel machine, having 2F64 set to 1 pays off, but it
doesn't for 2F32:
- Intel i7-6700K:
add-single: [1] 285.79 vs [0] 426.70 MFlops
add-double: [1] 302.15 vs [0] 278.82 MFlops
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
This commit is contained in:
Emilio G. Cota
Alex Bennée
parent
a94b783952
commit
1b615d4820
123
fpu/softfloat.c
123
fpu/softfloat.c
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@ -1054,24 +1054,6 @@ float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *status)
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return float16_round_pack_canonical(pr, status);
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}
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float32 QEMU_FLATTEN float32_add(float32 a, float32 b, float_status *status)
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{
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FloatParts pa = float32_unpack_canonical(a, status);
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FloatParts pb = float32_unpack_canonical(b, status);
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FloatParts pr = addsub_floats(pa, pb, false, status);
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return float32_round_pack_canonical(pr, status);
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}
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float64 QEMU_FLATTEN float64_add(float64 a, float64 b, float_status *status)
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{
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FloatParts pa = float64_unpack_canonical(a, status);
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FloatParts pb = float64_unpack_canonical(b, status);
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FloatParts pr = addsub_floats(pa, pb, false, status);
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return float64_round_pack_canonical(pr, status);
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}
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float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status)
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{
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FloatParts pa = float16_unpack_canonical(a, status);
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@ -1081,24 +1063,121 @@ float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status)
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return float16_round_pack_canonical(pr, status);
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}
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float32 QEMU_FLATTEN float32_sub(float32 a, float32 b, float_status *status)
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static float32 QEMU_SOFTFLOAT_ATTR
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soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status)
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{
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FloatParts pa = float32_unpack_canonical(a, status);
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FloatParts pb = float32_unpack_canonical(b, status);
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FloatParts pr = addsub_floats(pa, pb, true, status);
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FloatParts pr = addsub_floats(pa, pb, subtract, status);
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return float32_round_pack_canonical(pr, status);
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}
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float64 QEMU_FLATTEN float64_sub(float64 a, float64 b, float_status *status)
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static inline float32 soft_f32_add(float32 a, float32 b, float_status *status)
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{
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return soft_f32_addsub(a, b, false, status);
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}
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static inline float32 soft_f32_sub(float32 a, float32 b, float_status *status)
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{
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return soft_f32_addsub(a, b, true, status);
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}
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static float64 QEMU_SOFTFLOAT_ATTR
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soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status)
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{
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FloatParts pa = float64_unpack_canonical(a, status);
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FloatParts pb = float64_unpack_canonical(b, status);
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FloatParts pr = addsub_floats(pa, pb, true, status);
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FloatParts pr = addsub_floats(pa, pb, subtract, status);
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return float64_round_pack_canonical(pr, status);
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}
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static inline float64 soft_f64_add(float64 a, float64 b, float_status *status)
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{
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return soft_f64_addsub(a, b, false, status);
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}
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static inline float64 soft_f64_sub(float64 a, float64 b, float_status *status)
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{
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return soft_f64_addsub(a, b, true, status);
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}
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static float hard_f32_add(float a, float b)
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{
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return a + b;
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}
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static float hard_f32_sub(float a, float b)
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{
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return a - b;
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}
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static double hard_f64_add(double a, double b)
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{
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return a + b;
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}
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static double hard_f64_sub(double a, double b)
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{
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return a - b;
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}
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static bool f32_addsub_post(union_float32 a, union_float32 b)
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{
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if (QEMU_HARDFLOAT_2F32_USE_FP) {
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return !(fpclassify(a.h) == FP_ZERO && fpclassify(b.h) == FP_ZERO);
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}
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return !(float32_is_zero(a.s) && float32_is_zero(b.s));
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}
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static bool f64_addsub_post(union_float64 a, union_float64 b)
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{
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if (QEMU_HARDFLOAT_2F64_USE_FP) {
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return !(fpclassify(a.h) == FP_ZERO && fpclassify(b.h) == FP_ZERO);
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} else {
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return !(float64_is_zero(a.s) && float64_is_zero(b.s));
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}
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}
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static float32 float32_addsub(float32 a, float32 b, float_status *s,
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hard_f32_op2_fn hard, soft_f32_op2_fn soft)
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{
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return float32_gen2(a, b, s, hard, soft,
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f32_is_zon2, f32_addsub_post, NULL, NULL);
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}
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static float64 float64_addsub(float64 a, float64 b, float_status *s,
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hard_f64_op2_fn hard, soft_f64_op2_fn soft)
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{
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return float64_gen2(a, b, s, hard, soft,
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f64_is_zon2, f64_addsub_post, NULL, NULL);
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}
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float32 QEMU_FLATTEN
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float32_add(float32 a, float32 b, float_status *s)
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{
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return float32_addsub(a, b, s, hard_f32_add, soft_f32_add);
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}
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float32 QEMU_FLATTEN
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float32_sub(float32 a, float32 b, float_status *s)
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{
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return float32_addsub(a, b, s, hard_f32_sub, soft_f32_sub);
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}
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float64 QEMU_FLATTEN
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float64_add(float64 a, float64 b, float_status *s)
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{
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return float64_addsub(a, b, s, hard_f64_add, soft_f64_add);
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}
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float64 QEMU_FLATTEN
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float64_sub(float64 a, float64 b, float_status *s)
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{
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return float64_addsub(a, b, s, hard_f64_sub, soft_f64_sub);
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}
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/*
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* Returns the result of multiplying the floating-point values `a' and
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* `b'. The operation is performed according to the IEC/IEEE Standard
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