hw/arm/virt-acpi-build: IORT upgrade up to revision E.b
Upgrade the IORT table from B to E.b specification revision (ARM DEN 0049E.b). The SMMUv3 and root complex node have additional fields. Also unique IORT node identifiers are introduced: they are generated in sequential order. They are not cross-referenced though. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20211014115643.756977-3-eric.auger@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Eric Auger
Richard Henderson
parent
5384adef5d
commit
1c2cb7e0b3
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@ -241,19 +241,20 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
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#endif
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#define ID_MAPPING_ENTRY_SIZE 20
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#define SMMU_V3_ENTRY_SIZE 60
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#define ROOT_COMPLEX_ENTRY_SIZE 32
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#define SMMU_V3_ENTRY_SIZE 68
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#define ROOT_COMPLEX_ENTRY_SIZE 36
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#define IORT_NODE_OFFSET 48
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static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
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uint32_t id_count, uint32_t out_ref)
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{
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/* Identity RID mapping covering the whole input RID range */
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/* Table 4 ID mapping format */
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build_append_int_noprefix(table_data, input_base, 4); /* Input base */
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build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */
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build_append_int_noprefix(table_data, input_base, 4); /* Output base */
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build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
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build_append_int_noprefix(table_data, 0, 4); /* Flags */
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/* Flags */
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build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4);
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}
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struct AcpiIortIdMapping {
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@ -298,7 +299,7 @@ static int iort_idmap_compare(gconstpointer a, gconstpointer b)
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/*
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* Input Output Remapping Table (IORT)
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* Conforms to "IO Remapping Table System Software on ARM Platforms",
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* Document number: ARM DEN 0049B, October 2015
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* Document number: ARM DEN 0049E.b, Feb 2021
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*/
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static void
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build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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@ -307,10 +308,11 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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const uint32_t iort_node_offset = IORT_NODE_OFFSET;
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size_t node_size, smmu_offset = 0;
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AcpiIortIdMapping *idmap;
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uint32_t id = 0;
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GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
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GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
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AcpiTable table = { .sig = "IORT", .rev = 0, .oem_id = vms->oem_id,
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AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
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.oem_table_id = vms->oem_table_id };
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/* Table 2 The IORT */
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acpi_table_begin(&table, table_data);
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@ -358,12 +360,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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/* 3.1.1.3 ITS group node */
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/* Table 12 ITS Group Format */
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build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
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node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
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build_append_int_noprefix(table_data, node_size, 2); /* Length */
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build_append_int_noprefix(table_data, 0, 1); /* Revision */
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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build_append_int_noprefix(table_data, 1, 1); /* Revision */
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build_append_int_noprefix(table_data, id++, 4); /* Identifier */
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build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
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build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
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build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
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@ -374,19 +376,19 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
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smmu_offset = table_data->len - table.table_offset;
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/* 3.1.1.2 SMMUv3 */
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/* Table 9 SMMUv3 Format */
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build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
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node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
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build_append_int_noprefix(table_data, node_size, 2); /* Length */
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build_append_int_noprefix(table_data, 0, 1); /* Revision */
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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build_append_int_noprefix(table_data, 4, 1); /* Revision */
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build_append_int_noprefix(table_data, id++, 4); /* Identifier */
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build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */
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/* Reference to ID Array */
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build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
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/* Base address */
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build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
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/* Flags */
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build_append_int_noprefix(table_data, 1 /* COHACC OverrideNote */, 4);
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build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4);
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
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/* Model */
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@ -395,35 +397,43 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
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build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
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build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
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build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */
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/* DeviceID mapping index (ignored since interrupts are GSIV based) */
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build_append_int_noprefix(table_data, 0, 4);
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/* output IORT node is the ITS group node (the first node) */
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build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
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}
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/* Table 16 Root Complex Node */
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/* Table 17 Root Complex Node */
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build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
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node_size = ROOT_COMPLEX_ENTRY_SIZE +
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ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
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build_append_int_noprefix(table_data, node_size, 2); /* Length */
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build_append_int_noprefix(table_data, 0, 1); /* Revision */
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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build_append_int_noprefix(table_data, 3, 1); /* Revision */
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build_append_int_noprefix(table_data, id++, 4); /* Identifier */
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/* Number of ID mappings */
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build_append_int_noprefix(table_data, rc_mapping_count, 4);
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/* Reference to ID Array */
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build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
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/* Table 13 Memory access properties */
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/* Table 14 Memory access properties */
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/* CCA: Cache Coherent Attribute */
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build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
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build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
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build_append_int_noprefix(table_data, 0, 2); /* Reserved */
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/* MAF: Note Memory Access Flags */
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build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DCAS = 1 */, 1);
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/* Table 15 Memory Access Flags */
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build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1);
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build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */
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/* MCFG pci_segment */
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build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
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/* Memory address size limit */
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build_append_int_noprefix(table_data, 64, 1);
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build_append_int_noprefix(table_data, 0, 3); /* Reserved */
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/* Output Reference */
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if (vms->iommu == VIRT_IOMMU_SMMUV3) {
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AcpiIortIdMapping *range;
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