FDC fix 5/10 (Hervé Poussineau):
- Better handling of DOR register. DOR register drives external motors, but it not limited to existing drives. - Use FD_DOR_nRESET flag instead of internal FD_CTRL_RESET flag. - Support writing to DOR register even in reset mode (as said in specification) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4285 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
368df94d16
commit
1c346df2a2
94
hw/fdc.c
94
hw/fdc.c
@ -69,10 +69,6 @@ typedef enum fdrive_type_t {
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FDRIVE_DRV_NONE = 0x03, /* No drive connected */
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} fdrive_type_t;
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typedef enum fdrive_flags_t {
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FDRIVE_MOTOR_ON = 0x01, /* motor on/off */
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} fdrive_flags_t;
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typedef enum fdisk_flags_t {
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FDISK_DBL_SIDES = 0x01,
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} fdisk_flags_t;
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@ -81,7 +77,6 @@ typedef struct fdrive_t {
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BlockDriverState *bs;
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/* Drive status */
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fdrive_type_t drive;
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fdrive_flags_t drflags;
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uint8_t perpendicular; /* 2.88 MB access mode */
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/* Position */
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uint8_t head;
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@ -103,7 +98,6 @@ static void fd_init (fdrive_t *drv, BlockDriverState *bs)
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/* Drive */
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drv->bs = bs;
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drv->drive = FDRIVE_DRV_NONE;
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drv->drflags = 0;
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drv->perpendicular = 0;
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/* Disk */
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drv->last_sect = 0;
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@ -296,24 +290,6 @@ static void fd_revalidate (fdrive_t *drv)
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}
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}
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/* Motor control */
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static void fd_start (fdrive_t *drv)
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{
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drv->drflags |= FDRIVE_MOTOR_ON;
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}
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static void fd_stop (fdrive_t *drv)
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{
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drv->drflags &= ~FDRIVE_MOTOR_ON;
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}
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/* Re-initialise a drives (motor off, repositioned) */
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static void fd_reset (fdrive_t *drv)
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{
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fd_stop(drv);
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fd_recalibrate(drv);
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}
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation */
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@ -337,7 +313,6 @@ static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
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enum {
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FD_CTRL_ACTIVE = 0x01, /* XXX: suppress that */
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FD_CTRL_RESET = 0x02,
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FD_CTRL_SLEEP = 0x04, /* XXX: suppress that */
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FD_CTRL_BUSY = 0x08, /* dma transfer in progress */
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};
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@ -621,10 +596,6 @@ static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
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static void fd_save (QEMUFile *f, fdrive_t *fd)
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{
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uint8_t tmp;
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tmp = fd->drflags;
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qemu_put_8s(f, &tmp);
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qemu_put_8s(f, &fd->head);
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qemu_put_8s(f, &fd->track);
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qemu_put_8s(f, &fd->sect);
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@ -662,10 +633,6 @@ static void fdc_save (QEMUFile *f, void *opaque)
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static int fd_load (QEMUFile *f, fdrive_t *fd)
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{
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uint8_t tmp;
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qemu_get_8s(f, &tmp);
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fd->drflags = tmp;
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qemu_get_8s(f, &fd->head);
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qemu_get_8s(f, &fd->track);
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qemu_get_8s(f, &fd->sect);
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@ -773,7 +740,7 @@ static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
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if (!fdctrl->drives[1].bs)
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fdctrl->sra |= FD_SRA_nDRV2;
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fdctrl->cur_drv = 0;
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fdctrl->dor = 0;
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fdctrl->dor = FD_DOR_nRESET;
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fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
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fdctrl->msr = 0;
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/* FIFO state */
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@ -782,7 +749,7 @@ static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
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fdctrl->data_state = FD_STATE_CMD;
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fdctrl->data_dir = FD_DIR_WRITE;
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for (i = 0; i < MAX_FD; i++)
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fd_reset(&fdctrl->drives[i]);
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fd_recalibrate(&fdctrl->drives[i]);
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fdctrl_reset_fifo(fdctrl);
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if (do_irq)
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fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
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@ -826,19 +793,8 @@ static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
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/* Digital output register : 0x02 */
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static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
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{
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uint32_t retval = 0;
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uint32_t retval = fdctrl->dor;
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/* Drive motors state indicators */
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if (drv0(fdctrl)->drflags & FDRIVE_MOTOR_ON)
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retval |= FD_DOR_MOTEN0;
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if (drv1(fdctrl)->drflags & FDRIVE_MOTOR_ON)
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retval |= FD_DOR_MOTEN1;
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/* DMA enable */
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if (fdctrl->dor & FD_DOR_DMAEN)
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retval |= FD_DOR_DMAEN;
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/* Reset indicator */
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if (!(fdctrl->state & FD_CTRL_RESET))
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retval |= FD_DOR_nRESET;
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/* Selected drive */
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retval |= fdctrl->cur_drv;
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FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
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@ -848,13 +804,6 @@ static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
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static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
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{
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/* Reset mode */
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if (fdctrl->state & FD_CTRL_RESET) {
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if (!(value & FD_DOR_nRESET)) {
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FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
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return;
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}
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}
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FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
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/* Motors */
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@ -873,31 +822,16 @@ static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
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else
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fdctrl->srb &= ~FD_SRB_DR0;
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/* Drive motors state indicators */
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if (value & FD_DOR_MOTEN1)
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fd_start(drv1(fdctrl));
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else
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fd_stop(drv1(fdctrl));
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if (value & FD_DOR_MOTEN0)
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fd_start(drv0(fdctrl));
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else
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fd_stop(drv0(fdctrl));
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/* DMA enable */
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#if 0
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if (fdctrl->dma_chann != -1)
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fdctrl->dma_en = value & FD_DOR_DMAEN ? 1 : 0;
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#endif
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/* Reset */
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if (!(value & FD_DOR_nRESET)) {
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if (!(fdctrl->state & FD_CTRL_RESET)) {
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if (fdctrl->dor & FD_DOR_nRESET) {
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FLOPPY_DPRINTF("controller enter RESET state\n");
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fdctrl->state |= FD_CTRL_RESET;
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}
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} else {
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if (fdctrl->state & FD_CTRL_RESET) {
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if (!(fdctrl->dor & FD_DOR_nRESET)) {
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FLOPPY_DPRINTF("controller out of RESET state\n");
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fdctrl_reset(fdctrl, 1);
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fdctrl->state &= ~(FD_CTRL_RESET | FD_CTRL_SLEEP);
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fdctrl->state &= ~FD_CTRL_SLEEP;
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}
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}
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/* Selected drive */
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@ -922,7 +856,7 @@ static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
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static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
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{
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/* Reset mode */
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if (fdctrl->state & FD_CTRL_RESET) {
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if (!(fdctrl->dor & FD_DOR_nRESET)) {
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FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
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return;
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}
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@ -937,7 +871,8 @@ static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
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{
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uint32_t retval = 0;
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fdctrl->state &= ~(FD_CTRL_SLEEP | FD_CTRL_RESET);
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fdctrl->dor |= FD_DOR_nRESET;
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fdctrl->state &= ~FD_CTRL_SLEEP;
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if (!(fdctrl->state & FD_CTRL_BUSY)) {
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/* Data transfer allowed */
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retval |= FD_MSR_RQM;
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@ -959,16 +894,16 @@ static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
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static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
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{
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/* Reset mode */
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if (fdctrl->state & FD_CTRL_RESET) {
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if (!(fdctrl->dor & FD_DOR_nRESET)) {
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FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
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return;
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}
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FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
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/* Reset: autoclear */
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if (value & FD_DSR_SWRESET) {
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fdctrl->state |= FD_CTRL_RESET;
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fdctrl->dor &= ~FD_DOR_nRESET;
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fdctrl_reset(fdctrl, 1);
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fdctrl->state &= ~FD_CTRL_RESET;
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fdctrl->dor |= FD_DOR_nRESET;
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}
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if (value & FD_DSR_PWRDOWN) {
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fdctrl->state |= FD_CTRL_SLEEP;
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@ -1618,7 +1553,6 @@ static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
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fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
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cur_drv = get_cur_drv(fdctrl);
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fd_start(cur_drv);
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if (fdctrl->fifo[2] <= cur_drv->track)
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cur_drv->dir = 1;
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else
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@ -1692,7 +1626,6 @@ static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
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fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
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cur_drv = get_cur_drv(fdctrl);
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fd_start(cur_drv);
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cur_drv->dir = 0;
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if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
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cur_drv->track = cur_drv->max_track - 1;
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@ -1709,7 +1642,6 @@ static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
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fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
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cur_drv = get_cur_drv(fdctrl);
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fd_start(cur_drv);
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cur_drv->dir = 1;
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if (fdctrl->fifo[2] > cur_drv->track) {
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cur_drv->track = 0;
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@ -1772,7 +1704,7 @@ static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
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cur_drv = get_cur_drv(fdctrl);
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/* Reset mode */
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if (fdctrl->state & FD_CTRL_RESET) {
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if (!(fdctrl->dor & FD_DOR_nRESET)) {
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FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
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return;
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}
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