OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC 

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Inès Varhol 2024-03-05 22:03:11 +01:00 committed by Peter Maydell
parent 1cdcfb6e93
commit 1c38129de8
6 changed files with 63 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/arm/Kconfig
View File

@ -473,9 +473,10 @@ config STM32L4X5_SOC
bool
select ARM_V7M
select OR_IRQ
select STM32L4X5_SYSCFG
select STM32L4X5_EXTI
select STM32L4X5_SYSCFG
select STM32L4X5_RCC
select STM32L4X5_GPIO
config XLNX_ZYNQMP_ARM
bool

71
hw/arm/stm32l4x5_soc.c
View File

@ -28,6 +28,7 @@
#include "sysemu/sysemu.h"
#include "hw/or-irq.h"
#include "hw/arm/stm32l4x5_soc.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
@ -99,6 +100,22 @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = {
16, 35, 36, 37, 38,
};
static const struct {
uint32_t addr;
uint32_t moder_reset;
uint32_t ospeedr_reset;
uint32_t pupdr_reset;
} stm32l4x5_gpio_cfg[NUM_GPIOS] = {
{ 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
{ 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
{ 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
{ 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },
{ 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },
{ 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },
{ 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
{ 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
};
static void stm32l4x5_soc_initfn(Object *obj)
{
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
@ -110,6 +127,11 @@ static void stm32l4x5_soc_initfn(Object *obj)
}
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
for (unsigned i = 0; i < NUM_GPIOS; i++) {
g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
}
}
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
@ -118,8 +140,9 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
MemoryRegion *system_memory = get_system_memory();
DeviceState *armv7m;
DeviceState *armv7m, *dev;
SysBusDevice *busdev;
uint32_t pin_index;
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
sc->flash_size, errp)) {
@ -160,17 +183,43 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
/* GPIOs */
for (unsigned i = 0; i < NUM_GPIOS; i++) {
g_autofree char *name = g_strdup_printf("%c", 'A' + i);
dev = DEVICE(&s->gpio[i]);
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint32(dev, "mode-reset",
stm32l4x5_gpio_cfg[i].moder_reset);
qdev_prop_set_uint32(dev, "ospeed-reset",
stm32l4x5_gpio_cfg[i].ospeedr_reset);
qdev_prop_set_uint32(dev, "pupd-reset",
stm32l4x5_gpio_cfg[i].pupdr_reset);
busdev = SYS_BUS_DEVICE(&s->gpio[i]);
g_free(name);
name = g_strdup_printf("gpio%c-out", 'a' + i);
qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk",
qdev_get_clock_out(DEVICE(&(s->rcc)), name));
if (!sysbus_realize(busdev, errp)) {
return;
}
sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);
}
/* System configuration controller */
busdev = SYS_BUS_DEVICE(&s->syscfg);
if (!sysbus_realize(busdev, errp)) {
return;
}
sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
/*
* TODO: when the GPIO device is implemented, connect it
* to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
* GPIO_NUM_PINS.
*/
for (unsigned i = 0; i < NUM_GPIOS; i++) {
for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {
pin_index = GPIO_NUM_PINS * i + j;
qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j,
qdev_get_gpio_in(DEVICE(&s->syscfg),
pin_index));
}
}
/* EXTI device */
busdev = SYS_BUS_DEVICE(&s->exti);
@ -217,7 +266,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
}
}
for (unsigned i = 0; i < 16; i++) {
for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {
qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
qdev_get_gpio_in(DEVICE(&s->exti), i));
}
@ -302,14 +351,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
/* RESERVED: 0x40024400, 0x7FDBC00 */
/* AHB2 BUS */
create_unimplemented_device("GPIOA", 0x48000000, 0x400);
create_unimplemented_device("GPIOB", 0x48000400, 0x400);
create_unimplemented_device("GPIOC", 0x48000800, 0x400);
create_unimplemented_device("GPIOD", 0x48000C00, 0x400);
create_unimplemented_device("GPIOE", 0x48001000, 0x400);
create_unimplemented_device("GPIOF", 0x48001400, 0x400);
create_unimplemented_device("GPIOG", 0x48001800, 0x400);
create_unimplemented_device("GPIOH", 0x48001C00, 0x400);
/* RESERVED: 0x48002000, 0x7FDBC00 */
create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);
create_unimplemented_device("ADC", 0x50040000, 0x400);

1
hw/misc/stm32l4x5_syscfg.c
View File

@ -27,6 +27,7 @@
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "hw/misc/stm32l4x5_syscfg.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#define SYSCFG_MEMRMP 0x00
#define SYSCFG_CFGR1 0x04

2
include/hw/arm/stm32l4x5_soc.h
View File

@ -30,6 +30,7 @@
#include "hw/misc/stm32l4x5_syscfg.h"
#include "hw/misc/stm32l4x5_exti.h"
#include "hw/misc/stm32l4x5_rcc.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#include "qom/object.h"
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
@ -49,6 +50,7 @@ struct Stm32l4x5SocState {
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
Stm32l4x5SyscfgState syscfg;
Stm32l4x5RccState rcc;
Stm32l4x5GpioState gpio[NUM_GPIOS];
MemoryRegion sram1;
MemoryRegion sram2;

1
include/hw/gpio/stm32l4x5_gpio.h
View File

@ -25,6 +25,7 @@
#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
#define NUM_GPIOS 8
#define GPIO_NUM_PINS 16
struct Stm32l4x5GpioState {

3
include/hw/misc/stm32l4x5_syscfg.h
View File

@ -26,12 +26,11 @@
#include "hw/sysbus.h"
#include "qom/object.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
#define NUM_GPIOS 8
#define GPIO_NUM_PINS 16
#define SYSCFG_NUM_EXTICR 4
struct Stm32l4x5SyscfgState {